Pulse or digital communications – Receivers – Automatic gain control
Reexamination Certificate
1998-01-09
2001-04-03
Chin, Stephen (Department: 2734)
Pulse or digital communications
Receivers
Automatic gain control
C455S239100
Reexamination Certificate
active
06212244
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to spread-spectrum communications, and more particularly to a two-step fast automatic-gain-control (AGC) loop capable of adjusting the gain of an AGC amplifier to compensate for large variations in received signal power.
DESCRIPTION OF THE RELEVANT ART
The evolution of telecommunications to very high data rates with packet transmissions over the air has imposed great constraints on the receiving system radio frequency (RF) stages as well as on the operation of the analog-to-digital converters in the case of digital communications. Due to large variations in received signal power caused by propagation attenuation, a control mechanism is required, by which the gain of a receiving amplifier is altered so that subsequent RF sections and/or digital sections of the receiving system operate close to an optimum operating point. These sections include amplifiers, mixers, analog-to-digital converters and baseband analog or digital processing devices. The control mechanism for adjusting the amplification of the received signal level is referred to as the automatic-gain-control (AGC) circuit.
The requirement of the AGC circuit is to keep the amplified received signal at a constant level over a large dynamic range of received signal power levels. The three main parameters when designing an AGC circuit are its operational range, its response time and its steady-state error. The operational range of an AGC circuit can easily exceed 70 dB or 80 dB in signal power.
Normally, in dynamic systems, the response time of the system is inversely proportional to its steady state error. In high data rate digital communications, and especially in packet switched systems, the conflict between these last two parameters becomes increasingly important. In these types of systems, the data transmission interval could be as small as a few hundred microseconds, if not a few tens of microseconds. In these cases, the system should adjust the gain of the received signal during only a small portion at the onset of signal reception, and operate with the smallest possible error during the remainder of the data reception.
SUMMARY OF THE INVENTION
A general object of the invention is to receive spread-spectrum signals having large variations in received signal power, caused by propagation, multipath, and other effects on a signal propagating over a communications channel.
Another object of the invention is to keep the amplified received signal at a constant level over a large range of received signal power levels.
According to the present invention, as embodied and broadly described herein, a two-step fast automatic-gain-control (AGC) loop, for use with a receiver, is provided. The first step is a coarse adjustment and the second step is a fine adjustment.
The AGC loop broadly includes an AGC amplifier, a received-signal-strength-indicator (RSSI) circuit, an RSSI-mapping circuit, an AGC-storing circuit, a converter circuit, an error circuit, an integrate-and-dump circuit and a normalizing circuit. The AGC amplifier has an AGC gain, and amplifies a received signal. The received signal, in a preferred embodiment, is a packet-spread-spectrum signal. A packet-spread-spectrum signal, as used herein, is a spread-spectrum signal transmitted by one or more transmitters, and arriving at the input of one or more receivers.
The packet-spread-spectrum signal includes a header concatenated with at least one channel of a spread-spectrum signal. For one channel, the header is concatenated with a single channel, spread-spectrum signal. The header, alternatively, may be concatenated with a multichannel, spread-spectrum signal. Timing may be triggered from the header part of the packet-spread-spectrum signal. For the case of the packet-spread-spectrum signal, each packet has the header followed in time by the channel of the spread-spectrum signal. The header and the channel of the spread-spectrum signal are sent as the packet-spread-spectrum signal, and the timing for the channel of the spread-spectrum signal, and thus the data, in the packet-spread-spectrum signal is keyed from the header. The data in the channel of the spread-spectrum signal may contain information such as digitized voice, signaling, adaptive power control (APC), cyclic-redundancy-check (CRC) code, etc.
The header, or preamble, is generated from spread-spectrum processing a header-symbol-sequence signal with a chip-sequence signal. The channel part of the packet-spread-spectrum signal is generated from spread-spectrum processing a data-sequence signal with a chip-sequence signal, or a plurality of data-sequence signals with a plurality of chip-sequence signals, respectively.
At each of the receivers, the translating device, e.g., down converter, translates the received packet-spread-spectrum signal from the carrier frequency to a processing frequency. The processing frequency may be at a radio frequency (RF), intermediate frequency (IF) or at baseband frequency. The processing frequency is a design choice, and any of the frequency ranges may be used by the invention.
For coarse adjustment using the AGC loop, the RSSI circuit generates, from an output signal from the AGC amplifier, an RSSI signal proportional to a received-signal-power level of the received signal. The RSSI-mapping circuit has an RSSI-mapping table. From the RSSI signal, the RSSI-mapping circuit, using the RSSI-mapping table, generates an AGC signal.
The AGC-storing circuit stores the AGC signal. Using the value of the stored-AGC signal, the AGC amplifier adjusts the AGC gain.
For many systems, the coarse adjustment requires finer adjustment. For fine adjustment using the AGC loop, the converter circuit converts the output signal from the AGC amplifier to an in-phase component and a quadrature-phase component at a processing frequency. The error circuit determines an error signal from the in-phase component and the quadrature-phase component. In response to the error signal indicating that both the in-phase component and the quadrature-phase component are high, the integrate-and-dump circuit increments a counter of the integrate-and-dump circuit. In response to the error signal indicating that both the in-phase component and the quadrature-phase component are low, the integrate-and-dump circuit decrements the counter of the integrate-and-dump circuit. In response to the error signal indicating the in-phase component and the quadrature-phase component are different, the integrate-and-dump circuit does not change the counter of the integrate-and-dump circuit. An output signal from the integrate-and-dump circuit is denoted an I&D signal.
The normalizing circuit, which may be embodied as an AGC-convergence-rate multiplier, normalizes the I&D signal. The output of the normalizing circuit is called a normalized signal.
The AGC-storing circuit updates the stored-AGC signal from the normalized signal. Using the updated AGC signal, the AGC circuit adjusts the AGC gain.
The present invention also includes a two-step fast automatic-gain-control (AGC) method, for use with a receiver. The method uses an AGC amplifier with an AGC gain. The method comprises the steps of amplifying, with the AGC amplifier, a received signal and generating a received-signal-strength-indicator (RSSI) signal proportional to a received-signal-power level of the received signal. The method includes the steps of mapping, using an RSSI mapping table, an AGC signal; storing the AGC signal; and adjusting, in response to the stored-AGC signal, the AGC gain of the AGC amplifier.
When finer adjustment is necessary, the method further includes the steps of converting an output signal from the AGC amplifier to an in-phase component and a quadrature-phase component at a processing frequency; determining an error signal from the in-phase component and the quadrature-phase component; incrementing, in response to the error signal indicating both the in-phase component and the quadrature-phase component are high, a counter of the integrate-and-dump circuit; decrementing, in response to the error signal
Davidovici Sorin
Hama Norio
Iida Izumi
Kanterakis Emmanuel
Kenmochi Nobuhiko
Chin Stephen
Golden Bridge Technology Inc.
McDermott & Will & Emery
Rupert Paul N
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