Fast regular multiplier architecture

Details Fast regular multiplier architecture Fast regular multiplier architecture

1997-10-28

2000-02-22

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708630, G06F 752

Patent

active

060291877

ABSTRACT:
A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when reduced to silicon. A Hekstra-type multiplier is modified by replacing full adders circuits with compressor circuits in a manner that preserves the balance of the signal propagation delays. The result is an architecture having a regular layout that greatly facilitates its implementation in silicon.

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G.J. Hekstra et al., "A Fast Parallel Multiplier Architecture", Proceedings of IEEE Symposium on Circuits and Systems, pp. 2128-2131, 1992.
T. Sakuta et al., "Delay Balanced Multipliers for Low Power/Low Voltage DSP Core", IEEE Symposium on Low Power Electronics: Digest of Technical Papers, pp. 36-37, Oct. 1995.

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