Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-11-28
2002-05-21
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230050, C365S189020, C365S210130, C365S154000, C365S156000, C365S203000
Reexamination Certificate
active
06392957
ABSTRACT:
BACKGROUND
A. Technical Field
The present invention relates generally to the field of memory logic devices, and more specifically to memory devices having self-timed control logic. More particularly, the present invention relates to memory devices having self-timed write control logic. Still more particularly, the present invention relates to memory devices that have self-timed read control logic and self-timed write control logic.
B. Background of the Invention
Memory devices are well known in the semiconductor industry. The integration of memory cores with other circuitry has increased dramatically due to the proliferation and popularity of Application Specific Integrated Circuits (ASICs). New find improved designs for memory arrays such as for system-on-a-chip applications have increased the demand for shorter write cycle times. Thus, there is a need for memory cores or array designs that implement faster write cycles.
A typical prior art memory device
100
is shown in FIG.
1
. As can be seen, the prior art memory device
100
includes an X-decoder
102
, a word-line driver
104
, a memory cell array
106
, a reference column
108
, control logic
110
, pre-charge circuits
112
, and sense amplifiers
114
. A typical prior art device also includes a reference decoder
116
, a reference word-line driver
118
, a reference cell
120
and a reference sense amplifier
122
. In prior art memory devices, the reference cell
120
is used to detect the completion of a read cycle or write cycle for the memory array
106
. When the reference sense amplifier
122
detects that a read cycle or write cycle is complete for the memory array
106
, the reference sense amplifier
122
sends a signal to the control logic
110
. More specifically, the reference sense amplifier
122
sends a signal to a self-timed clock (STCLK) (not shown) in the control logic
110
that in turn sends a signal to the pre-charge circuits
112
. The pre-charge circuits
112
pre-charge the bit lines of the memory cells (not shown) in the memory array
106
so that the next read cycle or write cycle for the memory array
106
may begin.
A timing diagram illustrating signals for the detection of a read cycle or write cycle and the pre-charging of memory cells in the prior art memory array
106
during normal operation of control logic
110
is shown in FIG.
2
.
Before a typical read cycle, the bit line (BL-Read) for memory cell is pre-charged to the VDD level as shown in
FIG. 2
by reference point A. During the read cycle, as the cell is read, the bit line is pulled down approximately 100 mV to 200 mV by a current of approximately 100 &mgr;A as indicated by reference point B. A reference bit line (RBL) is also pulled down similar to the bit line during the read cycle. Once the read cycle has completed as indicated by reference point B, pre-charging starts until the line is pre-charged as indicated by reference point C. Generally, the completion of a read cycle is indicated by the fact that the reference bit line (RBL) has activated the self-timed clock (STCLK) which in turn begins the pre-charging. At such a time, the read cycle can begin again. It should be noted that while the time required for the bit line to transition from reference point A to reference point B occurs relatively slowly, the pre-charging of the bit-line occurs very quickly because the bit line typically only needs to be charged approximately 100-200 mV.
In comparison, the state of the bit line (BL-Write) during a write cycle has much different timing. Again, before a typical write cycle, the bit line (BL-Write) for memory cell is pre-charged to the VDD level as shown in
FIG. 2
by reference point D. During the write cycle, as the cell is written, the bit line is pulled down; and the write cycle is complete as indicated by reference point E. However, in the prior art, pre-charging of BL-Write does not begin until reference point F, which is the point in time when the read cycle is complete. Only after both the read cycle and write cycle are complete will RBL activate STCLK, which in turn initiates the pre-charging of both BL-Read and BL-Write. Thus, in the prior art, there is only one mechanism for initiating the pre-charging of both BL-Read and BL-Write. Consequently, in the prior art there is a “dead time” in write cycles when the pre-charging of BL-Write could begin independently of BL-Read but does not. This is problematic because it unnecessarily increases the write cycle time in prior art memory arrays and ties the pre-charging of both BL-Read and BL-Write to the same trigger event. Yet another difficulty in the prior art is that typically pre-charging after a write requires much more time than pre-charging after a read cycle. Only after reference point G can another write or read cycle begin. It should be noted that the time required for the bit line to transition from reference point D to reference point E occurs relatively quickly because the write drivers pulling the bit line down are large. In addition, the time required for the bit line to transition from reference point F to reference point G is much longer than pre-charging from reference point B to reference point C, because it is charging from ground to VDD as opposed to pre-charging from the 100-200 mV below VDD to VDD. Accordingly, it is desirable to provide a memory device that provides a shorter write cycle time.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies and limitations of the prior art with a unique memory device that provides self-timed write control for a memory array. This is particularly advantageous because it minimizes the cycle time for access of the cells of the array. The memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the time of the memory access cycle. The second reference cell may be any one of a conventional memory cell or write reference logic.
These and other features and advantages of the present invention may be better understood by considering the following detailed description of preferred embodiments of the invention. In the course of this description, reference will be frequently made to the attached drawings.
REFERENCES:
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 5546355 (1996-08-01), Raatz et al.
patent: 5808960 (1998-09-01), McClure
patent: 5825691 (1998-10-01), McClure
patent: 5864696 (1999-01-01), McClure
patent: 6006339 (1999-12-01), McClure
patent: 6072732 (2000-06-01), McClure
patent: 6091629 (2000-07-01), Osada et al.
Kablanian Adam
Raszka Jaroslav
Roy Richard S.
Shubat Alexander
Tran Andrew Q.
Virage Logic Corporation
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