Fast propagation technique in CMOS integrated circuits

Details Fast propagation technique in CMOS integrated circuits Fast propagation technique in CMOS integrated circuits

1994-06-30

1996-05-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

326 17, 326 20, 326 82, H03B 100

Patent

active

055193447

ABSTRACT:
A fast propagation technique for use in CMOS circuits, whereby faster signal transition at an information carrying edge of a propagating signal is achieved at a cost of slower signal transition at the opposite edge. The technique of the present invention skews a size ratio of P-channel pull-up to N-channel pull-down transistors in the CMOS circuit to obtain much faster transition at one (rising or falling) edge of the signal and slower transition at the opposite edge. The fast propagation technique of the present invention is well suited for synchronous digital CMOS circuits such as synchronous RAMs.

REFERENCES:
patent: 4599528 (1986-07-01), Redfield
patent: 4670672 (1987-06-01), Ando et al.
patent: 4985643 (1991-01-01), Proebsting
patent: 5061864 (1991-10-01), Rogers
patent: 5149990 (1992-09-01), Yamazaki et al.
patent: 5247212 (1993-09-01), Vinal
patent: 5274277 (1993-12-01), Chan

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