Fast programmable divider with a new 5-gate flip-flop

Details Fast programmable divider with a new 5-gate flip-flop Fast programmable divider with a new 5-gate flip-flop

1975-02-18

1976-07-20

Zazworsky, John

328 46, 328 48, H03K 2100, H03K 2302

Patent

active

039709418

ABSTRACT:
An N-bit programmable divider comprising N "T" flip-flops, N load gates, N-2 enable gates, an output JK flip-flop and a least-significant-bit input inverter; the least-significant-bit flip-flop being enabled by Q of said output flip-flop, the second-least-significant-bit flip-flop being enabled by Q of said least-significant-bit flip-flip, each of said remaining T flip-flops being enabled by NORed Q outputs of all less-significant-bit flip-flops, said output flip-flop having a J input only when the outputs of said N T flip-flops are indicative of a count of 2 and having a K input only with a Q output of said output flip-flop; the divider being loaded by application during Q of the output flip-flop of the complement of the least-significant-bit signal to the clear of the least-significant-bit T flip-flop and higher-significant-bit signals to preset of respective higher-significant-bit T flip-flops.

REFERENCES:
patent: 3811092 (1974-05-01), Charbonnier
B407,357 1/1975, Segal 328/41.

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