Fast program to program verify method

Details Fast program to program verify method Fast program to program verify method

2005-02-15

2005-02-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S182000, C365S201000, C365S210130, C365S189070

Reexamination Certificate

active

06856545

ABSTRACT:
In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

REFERENCES:
patent: 5784316 (1998-07-01), Hirata
patent: 6009015 (1999-12-01), Sugiyama
patent: 6011725 (2000-01-01), Eitan
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 1215681 (2002-06-01), None
patent: 1345273 (2003-09-01), None
“Twin MONOS Cell with Dual Control Gates”, by Yutaka Hayashi et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.

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