Fast processor for multi-bit error correction codes

Details Fast processor for multi-bit error correction codes Fast processor for multi-bit error correction codes

1988-04-29

1990-05-22

MacDonald, Allen

Excavating

371 375, G06F 1110

Patent

active

049282808

ABSTRACT:
Apparatus and method for performing error checking and syndrome generation on multibit characters of blocks of messages. The characters are processed ad seriatim and the symbols or syndromes are accumulated until all characters of a block have been processed. The check symbols are concatenated with the associated message block while the check symbols are accumulated for the next block. If there is a nonzero syndrome, the accumulated syndromes can be extracted while the syndromes for a next block are being generated.

REFERENCES:
patent: 4450561 (1984-05-01), Gotze
patent: 4577237 (1986-03-01), Collins
patent: 4667326 (1987-05-01), Young
patent: 4758902 (1988-07-01), Okamoto
patent: 4763332 (1988-08-01), Glover

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