Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-06-29
2001-09-11
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S563000
Reexamination Certificate
active
06288576
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an interface arrangement including a very high speed pre-amplifier for operating with relatively small input signals and with high Common Mode Rejection [CMR]. More particularly, the invention relates to an interface arrangement including, between a differential pair of inputs and an output, the cascade connection of a differential pre-amplifier and a comparator.
Such an interface arrangement is generally known in the art as a fast Low Voltage Differential Signal [LVDS] circuit for interfacing electronic chips. The current standards for such a LVDS circuit specify a minimum switching threshold voltage for the small differential input signal, while the common mode input signal varies over a very large range, both at a very high frequency. Because of the small input signal, a high sensitivity is required from the interface arrangement. In the known interface arrangements, the comparator is a differential amplifier preceded by a very high-speed differential pre-amplifier with low and controlled gain. The pre-amplifier must amplify the differential signal and attenuate the common mode signal. A simple differential pair of either NMOS transistors or PMOS transistors is not able to work in this full input range. Therefore, two input differential pairs are generally put in parallel: a PMOS and a NMOS differential pair. The outputs of these two differential pairs are combined into the inputs of the comparator. Each differential pair spans a part of the input voltage range. In the middle of this voltage range both PMOS and NMOS input pairs are active, whilst for input voltages near to the ground or to the supply voltage, either only the PMOS inputs or only the NMOS inputs are active. As a consequence, the gain of the input pre-amplifier is not constant over the whole input voltage range. Traditional circuits to keep the gain constant are much too slow for complying the standard requirements and can thus not be used. Moreover, since the output of the known pre-amplifier is related to the ground or to the supply voltage, the design of the subsequent comparator or differential amplifier is more difficult. Also the offset changes between each region of operation and this has a direct impact on the signal skew.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an interface arrangement of the above known type but wherein the gain is constant over the relatively large input voltage range for a relatively small input signal.
According to the invention, this object is achieved due to the fact that said differential pre-amplifier comprises a first and a second half pre-amplifier, each of said half pre-amplifiers having a first and a second input and an output connected to a distinct input of said comparator, that the first input of said first half pre-amplifier is connected to a first input of said interface arrangement and is coupled to the output of said first half pre-amplifier via first input inverter means, whilst the second input of said first half pre-amplifier is connected to the second input of said interface arrangement and is coupled to said output via second input inverter means comprising current mirror means for inverting the output current of said second input inverter means with respect to the output current of said first input inverter means, that said second half pre-amplifier is similar to said first half pre-amplifier, and that the first input of said second half pre-amplifier is connected to the second input of said interface arrangement, whilst the second input of said second half pre-amplifier is connected to the first input of said interface arrangement.
In this way, opposite currents coming from the first and from the second input inverter means are provided to the output of each half pre-amplifier. Since the two half pre-amplifiers are oppositely connected with respect to each other, a very high common mode signal attenuation is obtained. The inverter means behaves as an amplifier with the full supply voltage as input range. As a result, the large common mode range can be covered. A very high-speed is also possible owing to the low skew between the signals and the signal input range can be as wide as the full supply voltage.
Another characteristic feature of the present invention is that said first input inverter means comprises a first NMOS transistor series connected with a first PMOS transistor between a first supply terminal and a second supply terminal, the first input of said interface arrangement being connected to the gate of each of said first NMOS and first PMOS transistors, and the junction point of said series connected transistors being connected to the output of said half pre-amplifier.
The present invention is further also characterized in that said second input inverter means comprises a first and a second inverting circuit, in that said first inverting circuit comprises a second NMOS transistor series connected with a mirror input PMOS transistor between the first and the second supply terminals, in that said second inverting circuit comprises a second PMOS transistor series connected with a mirror input NMOS transistor between said first and said second supply terminals, in that the second input of said interface arrangement is connected to the gate of each of said second NMOS and second PMOS transistors, in that said second input inverter means further comprises a mirror output NMOS transistor series connected with a mirror output PMOS transistor between said first and said second supply terminals, the gate and the drain of said mirror input PMOS transistor being connected to the gate of said mirror output PMOS transistor, and the gate and the drain of said mirror input NMOS transistor being connected to the gate of said mirror output NMOS transistor, and in that the junction point of said series connected mirror output transistors being connected to the output of said half pre-amplifier.
As the NMOS and PMOS transistors behave quadratically, the sum of their gains remains constant. As a result, the gain of the interface arrangement remains constant over the full range of the input voltage.
Also another characteristic feature of the present invention is that a current source is provided between the gate of said mirror input PMOS transistor and the gate of said mirror input NMOS transistor.
This current source, located between the two diode connected mirror input transistors, prevents these transistors from switching both off when one of them is switched off at the extremes of signal input range. In other words, the current source keeps the two current mirrors active. As a result of which the speed of the Common Mode Rejection [CMR] is high.
Yet another characteristic feature of the present invention is that each of said half pre-amplifier further includes output means comprising an output NMOS transistor series connected with an output PMOS transistor between the first and the second supply terminal, the gates of said output NMOS and PMOS transistors being connected to the output of said half pre-amplifier as well as their junction point.
The complementary transistors are so forming a short-circuited inverter. This circuit is equivalent to a voltage source in series with a resistor. The resistance thereof is inversely proportional to the transconductance gain of the inverter transistors. In this way, a controlled gain can be achieved. Moreover, the dc voltage at the half pre-amplifier output is then around the mid supply voltage. This is usually better for the comparator and for the skew performance of a subsequent circuit, that may for instance be a pulse shaper.
REFERENCES:
patent: 4617523 (1986-10-01), Taylor
patent: 5049761 (1991-09-01), Zitta
patent: 5469392 (1995-11-01), Ihara
patent: 5726592 (1998-03-01), Schulte et al.
patent: 5751186 (1998-05-01), Nakao
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 43 24 649 A1 (1994-03-01), None
patent: 0 588 544 A2 (1994-03-01), None
Alcatel
Sughrue Mion Zinn Macpeak & Seas, PLLC
Tran Toan
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