Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
Reexamination Certificate
2006-11-14
2006-11-14
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Stack based computer
C711S132000, C712S225000
Reexamination Certificate
active
07136990
ABSTRACT:
A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data stored into the cache. When a pop instruction is encountered, the apparatus uses the row and way values at the top of the stack to access the cache. In one embodiment, an offset of the most recent push data within the current cache line specified by the top row and way values is maintained. The offset is updated on each push or pop. If a pop overflows the offset, the top entry of the stack is popped. If a push underflows the offset, the row and way values are pushed onto the stack. The row, way, and offset values are subsequently compared with the actual pop address to determine whether incorrect data was provided.
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Davis E. Alan
Huffman James W.
IP-First, LLC.
Kim Kenneth S.
LandOfFree
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