Fast pipelined matrix multiplier

Details Fast pipelined matrix multiplier Fast pipelined matrix multiplier

1992-02-13

1993-04-20

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

052048306

ABSTRACT:
A circuit and algorithm for multiplying three matrices is disclosed having a first multiplication stage for multiplying a first matrix with a second matrix to produce an intermediate product matrix. Additionally, the circuit and algorithm have a second stage for multiplying a third matrix with the intermediate product matrix to compute the final product matrix. Each stage is provided with a plurality of bit processing element pipelines for generating the elements of the product matrix of that stage. In each stage, one pipeline is provided for generating each column of the product matrix and each pipeline within a stage operates in parallel with the other pipelines of that stage.

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Cho et al., "Fast Algorithm and Implementation of a 2-D Discrete Cosine Transform," IEEE Trans. on Cir. & Sysm., Mar., 1991, 297-305.

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