Fast pipelined 2-D discrete cosine transform architecture

Details Fast pipelined 2-D discrete cosine transform architecture Fast pipelined 2-D discrete cosine transform architecture

1993-09-15

1996-01-09

Envall, Jr., Roy N.

Boots, shoes, and leggings

364726, 364754, G06F 738, G06F 1500, G06F 1540

Patent

active

054834759

ABSTRACT:
A DCT circuit has a pre-processor stage which receives each element x.sub.ij i,j=1,2, . . . ,N, where N is an integer.gtoreq.4, of an input matrix X. The pre-processor stage simultaneously outputs Q.gtoreq.1 sequences of one or more columns of elements of a matrix A.sub.f having elements a.sub.ij =x.sub.ij +x.sub.(N-i+1)j i=1,2, . . . ,N/2, j=1,2, . . . ,N and Q.gtoreq.1 sequences of one or more columns of elements of a matrix A.sub.r having elements a.sub.ij =x.sub.(i-N/2)j -x.sub.(3N/2-i+1)j i=N/2+1, N/2+2, . . . ,N j=1,2, . . . ,N. The DCT circuit also has a 1-D DCT processing stage which simultaneously receives each of the 2Q sequences of elements outputted by the pre-processor stage, P sequences of one or more rows of elements of an N/2.times.N/2 DCT cosine coefficient matrix C.sub.1 and P sequences of rows of elements of an N/2.times.N/2 DCT cosine coefficient matrix C.sub.2. The 1-D DCT processing stage has K.gtoreq.1 column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Y.sub.o containing the elements Y.sub.ij i=1,3, . . . ,N j=1,2, . . . ,N, where ##EQU1## and K.gtoreq.1 column multiplication circuits which each simultaneously outputs a sequence of one or more vectors of elements of a matrix Y.sub.e comprising elements Y.sub.ij i=2,4, . . . ,N j=1,2, . . . ,N where ##EQU2##

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