Fast parity generator using complement pass-transistor logic

Details Fast parity generator using complement pass-transistor logic Fast parity generator using complement pass-transistor logic

1993-11-23

1997-03-04

Beausoliel, Jr., Robert W.

Excavating

371 492, G06F 1110

Patent

active

056087411

ABSTRACT:
The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.

REFERENCES:
patent: 3591786 (1971-07-01), Nelson
patent: 3697949 (1972-10-01), Carter et al.
patent: 3838393 (1974-09-01), Dao
patent: 4251884 (1981-02-01), Baun, Jr.
patent: 4775810 (1988-10-01), Suzuki et al.
patent: 4879675 (1989-11-01), Brodnax
patent: 5023480 (1991-06-01), Gieseke et al.

Affiliated with

Also associated with

Rating

Fast parity generator using complement pass-transistor logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fast parity generator using complement pass-transistor logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast parity generator using complement pass-transistor logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2152736