Excavating
Patent
1981-08-31
1984-04-17
Smith, Jerry
Excavating
371 51, G06F 1100
Patent
active
044438761
ABSTRACT:
Parity for the address of a low order zero in an input data word is generated directly from the input data rather than from the address of the low order zero. A find low order zero circuit (11) generates an address of the low order zero in the data word. Simultaneously with this operation a parity generating circuit (12) operates on the input data word to generate parity for the low order zero address. The parity generating circuit comprises a plurality of individual circuits (30 through 33) each of which operates on a different byte of the input data word. The individual circuits each generate a control signal (E.sub.a,E.sub.b . . . ) according to whether or not its byte contains a low order order zero, and a result signal (R.sub.a,R.sub.b . . . ) which represents the parity of the address of the low order zero, if any, in the byte taking into account the byte position in the input data word. Logic circuitry combines the control and result signals to form the overall parity for the low order zero address.
REFERENCES:
patent: 3531631 (1970-09-01), Burgess
patent: 3555255 (1971-01-01), Toy
patent: 3571580 (1971-03-01), Buchan et al.
patent: 3678259 (1972-07-01), Kyser
patent: 3944800 (1976-03-01), Beck et al.
Signetics, Logic, Memories, Interface, Analog, Microprocessor, Military, Data Manual, 1976 pp. 138, 145, 183.
Bell Telephone Laboratories Incorporated
Fleming Michael R.
Herndon J. W.
Phillips S. J.
Smith Jerry
LandOfFree
Fast parity generation for find low order zero circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast parity generation for find low order zero circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast parity generation for find low order zero circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-98754