Fast parity checking in cache tag memory

Details Fast parity checking in cache tag memory Fast parity checking in cache tag memory

1982-07-21

1984-11-13

Smith, Jerry

Excavating

G06F 1110

Patent

active

044830033

ABSTRACT:
A parity checking arrangement for tag information in a cache memory. Parity generation is performed on the input tag in parallel with tag memory lookup and then compared with the parity stored in tag memory in order to speed operation. A single parity generator also may be used for writing into tag memory.

REFERENCES:
patent: 3789204 (1974-01-01), Barlow
patent: 4197580 (1980-04-01), Chang et al.
IBM Technical Disclosure Bulletin, Distributed Address Checking, F. J. Aichelmann, 4/76, vol. 18, No. 11.
IBM Technical Disclosure Bulletin, Microcode Integrity Checking, P. Favre, Apr. 1978, vol. 20, No. 11B.

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