Fast page programming architecture and method in a...

Details Fast page programming architecture and method in a... Fast page programming architecture and method in a...

2005-04-26

2005-04-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185070, C365S230080

Reexamination Certificate

active

06885584

ABSTRACT:
A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

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