Fast overflow and underflow limiting circuit for signed adder

Details Fast overflow and underflow limiting circuit for signed adder Fast overflow and underflow limiting circuit for signed adder

1991-01-03

1992-11-17

Malzahn, David H.

Boots, shoes, and leggings

3647365, G06F 1100

Patent

active

051649144

ABSTRACT:
In a signed binary adder circuit, limiter control circuitry detects underflow and overflow conditions, and controls combinatorial result limiter circuits in each bit position to limit the result to predetermined values under such conditions, respectively. The limiter circuits employ OR-AND-INVERT logic (OAI) to provide the appropriate result bits without clock delay for fast limiting.

REFERENCES:
patent: 4722066 (1988-01-01), Armer et al.
patent: 4817047 (1989-03-01), Nishitani et al.
patent: 4819198 (1989-04-01), Noll et al.
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5038314 (1991-08-01), Kelleher

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