Fast operating multiplexer

Details Fast operating multiplexer Fast operating multiplexer

1999-07-29

2002-11-05

Kizou, Hassan (Department: 2662)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S366000

Reexamination Certificate

active

06477186

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiplexer, and particularly a multiplexer which converts parallel data signals of multiple bits into a serial data signal of multiple bits in synchronization with a clock signal.
2. Description of the Background Art
FIG. 9
is a block diagram showing a structure of a multiplexer in the prior art. Referring to
FIG. 9
, the multiplexer includes a quarter divider
31
, a control signal generating circuit
32
, D-flip-flops
33
-
36
and
38
, and a four-to-one selector
37
.
As shown in
FIG. 10
, quarter divider
31
includes a D-flip-flop
41
, and also include D-latches
42
and
43
which form a D-flip-flop
44
. Flip-flop
41
and latch
42
are of a negative edge type, and therefore issue data in response to a falling edge of a clock signal. Latch
43
is of a positive edge type, and therefore issues data in response to the rising edge of clock signal.
Flip-flop
41
receives clock signal CLK on its clock terminal C, and have an output terminal Q and an inverted output terminal QB which are connected to an inverted input terminal DB and an input terminal D, respectively. Accordingly, flip-flop
41
issues from its output terminal Q a clock signal CLK/2, which has half a frequency of clock signal CLK, and is inverted upon every falling of clock signal CLK.
Clock signal CLK/2 is applied to clock terminals C of latches
42
and
43
. Output terminal Q and inverted output terminal QB of latch
42
are connected to input terminal D and inverted input terminal DQ of latch
43
, respectively. Output terminal Q and inverted output terminal QB of latch
43
are connected to inverted input terminal DB and input terminal D of latch
42
, respectively. Accordingly, latches
42
and
43
issue clock signals &phgr;
1
-&phgr;
4
, which have four phases shifted from each other by ¼ of their period, respectively, and each have a frequency equal to ¼ of that of clock signal CLK. Clock signals &phgr;
1
-&phgr;
4
are supplied to control signal generating circuit
32
. Output signal &phgr;
2
(CLK/4) of latch
43
is applied to clock terminals C of flip-flops
33
-
36
.
Control signal generating circuit
32
includes four NOR gates
51
-
54
and four NAND gates
55
-
58
. Each of NOR gates
51
-
54
receives signals of two phases among clock signals &phgr;
1
-&phgr;
4
, and issues corresponding one of control signals S
1
-S
4
. Each of NAND gates
55
-
58
receives signals of two phases among clock signals &phgr;
1
-&phgr;
4
, and issues corresponding one of control signals S
1
B-S
4
B. Control signals S
1
-S
4
have frequencies equal to that of clock signal CLK/4, and successively attain “H” level for ¼ of the period. Signals S
1
B-S
4
B are inverted signals of signals S
1
-S
4
, respectively. Control signals S
1
-S
4
and S
1
B-S
4
B are applied to four-to-one selector
37
. In
FIG. 9
, signals S
1
B-S
4
B are not shown for simplicity reason.
Flip-flops
33
-
36
receive data D
1
-D
4
on their input terminals D, and also receive clock signal CLK on their clock terminals C, respectively. Flip-flops
33
-
36
are of the negative edge type, and issue input data D
1
-D
4
in response to the falling edge of clock signal CLK/4. Output data D
1
′-D
4
′ of flip-flops
33
-
36
are applied to four-to-one selector
37
.
Four-to-one selector
37
includes, as shown in
FIG. 11
, four input nodes N
1
-N
4
, four transfer gates
61
-
64
and an output node N
5
. Four input nodes N
1
-N
4
are supplied with output data D
1
′-D
4
′ of flip-flops
33
-
36
, respectively. Transfer gates
61
-
64
are connected between input nodes N
1
-N
4
and output node N
5
, respectively, and are turned on in response to the states that control signals S
1
-S
4
attain “H” level and control signals S
1
B-S
4
B attain “L” level, respectively. Accordingly, data D
1
′-D
4
′ are issued to output node N
5
in response to the states that control signals S
1
-S
4
attain “H” level and control signals S
1
B-S
4
B attain “L” level, respectively.
An output data SOUT of selector
37
is supplied to input terminal D of flip-flop
38
, which also receives clock signal CLK on its clock terminal C. Flip-flop
38
is of a negative edge type, and issues input data SOUT in response to the falling edge of clock signal CLK. The output data of flip-flop
38
forms output data DOUT of this multiplexer.
FIGS. 12A-12H
are time charts showing operations of the multiplexer shown in
FIGS. 9
to
11
. Quarter divider
31
produces a clock signal CLK/4 having a period four times larger than that of clock signal CLK. Clock signal CLK/4 is applied to clock terminals C of flip-flops
33
-
36
. Flip-flops
33
-
36
continuously issue the same data D
1
′-D
4
′ for one period of clock signal CLK/4 (during cycles 1 to cycle 4 in FIG.
12
).
Quarter divider
31
produces four clock signals &phgr;
1
-&phgr;
4
which have the same frequencies as clock signal CLK/4, and also have phases shifted from each other by a quarter of the period. Clock signals &phgr;
1
-&phgr;
4
are applied to control signal generating circuit
32
. Control signals generating circuit
32
produces control signals S
1
-S
4
which attain “H” level in cycles 1-4, respectively, as well as inverted signals S
1
B-S
4
B of them, and applies signals S
1
-S
4
and S
1
B-S
4
B to a selector
37
.
Transfer gates
61
-
64
of selector
37
are turned on during cycles 1-4 in accordance with S
1
and S
1
B, . . . , and S
4
and S
4
B, respectively. Accordingly, data D
1
_
1
-D
4
_
1
corresponding to data D
1
′-D
4
′ are issued in serial from output node N
5
of selector
37
to flip-flop
38
at every clock cycle, respectively.
Flip-flop
38
issues input data D
1
_
1
-D
4
_
1
in response to the falling edges of cycles 2 to 5, respectively. In this manner, slow parallel data D
1
-D
4
are converted into fast serial data D
1
_
1
-D
4
_
4
.
FIGS. 12A-12H
are time charts showing the operations in the case where each circuit included in the multiplexer does not have a delay time. However, each circuit included in the multiplexer practically has a delay time. Since quarter divider
31
has two flip-flops
41
and
44
, quarter divider
31
has the delay time of 2T_DFF equal to double the delay time T_DFF of each flip-flop. As shown in
FIGS. 13A-13D
, therefore, the phase of dock signal CLK_
4
is delayed by 2T_DFF from clock signal CLK.
The delay time of control signal generating circuit
32
is equal to a delay time T_NOR of an NOR gate because the delay time of the NOR gate is generally longer than that of an NAND gate. Accordingly, the phases of control signals S
1
-S
4
are delayed from clock signal CLK by (2T_DFF+T_NOR).
Assuming that selector
37
has a delay time of T_sel, a time of (2T_DFF+T_NOR+T_sel) is required from the input of clock signal CLK to the output from selector
37
, and a setup time T_setup of flip-flop
38
is required for taking in output data SOUT of selector
37
into flip-flop
38
. Therefore, a time of (2T_DFF+T_NOR+T_sel+T_setup) must fall within one clock cycle.
Accordingly, the multiplexer suffers from a problem that the maximum operation frequency fmax is restricted to or below the following value:
fmax=1/(2T_DFF+T_NOR+T_sel+T_setup)  (1)
SUMMARY OF THE INVENTION
Accordingly, a major object of the invention is to provide a fast-operating multiplexer, i.e., a multiplexer which can operate fast.
According to an aspect of the invention, a multiplexer includes a signal generating circuit for generating control signals of M phases, a first holding circuit for temporarily holding the control signals of M phases, and thereafter issuing the control signals in synchronization with a clock signal, a select circuit for converting parallel data signals of M bits into a serial data signal of M bits in response to the control signals of M phases, and a second holding circuit for temporarily holding each of output signals of the select circuit, a

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