Patent
1996-05-15
1998-08-18
Lim, Krisna
395394, G06F 938
Patent
active
057969973
ABSTRACT:
A fast nullify system and method facilitate handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are permitted to execute out of order. After execution of an instruction by an execution unit, instructions are retired by a retire mechanism, which transforms the results of instruction execution to the architecture state. While instructions are executed in the reordering mechanism nullifying instructions and dependent instructions that can potentially be nullified by the nullifying instructions are identified. For each dependent instruction, a determination is made as to whether the dependent instruction qualifies for a fast nullify procedure in that the dependent instruction has less operands than a number that can be read by the execution unit. When a dependent instruction qualifies, then the qualified dependent instruction and its corresponding nullifying instruction are permitted to execute substantially concurrently. During execution of the dependent instruction, the execution unit reads a previous result of a target register associated with the dependent instruction. The current result of the dependent instruction is stored in the target register when the dependent instruction is not nullified by the nullifying instruction. In contrast, the previous result is maintained in the target register when the dependent instruction is nullified by the nullifying instruction.
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Lesartre Gregg
Lotz Jonathan
Hewlett--Packard Company
Lim Krisna
Vu Viet
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