Boots – shoes – and leggings
Patent
1987-09-14
1989-06-13
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 752
Patent
active
048398489
ABSTRACT:
A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell includes an AND gate for producing single power product terms by multiplying together one bit from each of the two numbers. These cells are arranged in the arrays such that the total quantity of single power product terms of any particular power in the respective arrays is within 30% of each other. One subset of cells of each array also includes a respective two-bit adder, and another subset of cells of each array includes a respective three-bit adder. These two-bit and three-bit adders are interconnected within each array to form an intermediate result, in parallel with the other arrays, which consists of a partial sum of all product terms in the array together with no more than one remaining carry-in for each bit of that partial sum. All of these intermediate results are then added by parallel input adders to produce the product of the two numbers.
REFERENCES:
patent: 3670956 (1972-06-01), Calhoun
patent: 4598382 (1986-07-01), Sato
patent: 4706210 (1987-11-01), Snelling et al.
Peterson LuVerne R.
Rehart Michael A.
Fassbender Charles J.
Harkcom Gary V.
Miller Kenneth L.
Nguyen Long Than
Unisys Corporation
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