Fast method of floating-point multiplication and accumulation

Details Fast method of floating-point multiplication and accumulation Fast method of floating-point multiplication and accumulation

1995-10-17

1999-02-02

Ngo, Chuong Dinh

Boots, shoes, and leggings

36474811, G06F 738

Patent

active

058674136

ABSTRACT:
A fast floating-point multiplication and accumulation unit (fmac) is described. The described fmac uses significantly less hardware, thereby yielding a fast and an inexpensive fmac. This fmac uses an m-bit carry propagation adder instead of a 3 m-bit carry propagation adder and a 2 m-bit normalizer instead of a 3 m-bit normalizer. The normalizer relies on a leading one detection, as opposed to leading one/zero prediction used in known fmac's. Even when the product of the multiplication is opposite in sign to the number added to the product, the fmac, disclosed here, only uses an m-bit adder and a 2 m-bit normalizer.

REFERENCES:
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patent: 5241493 (1993-08-01), Chu et al.
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patent: 5471410 (1995-11-01), Bailey et al.
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Article by Montoye et al. entitled "Design of the IBM RISC System/6000 Floating-point Execution Unit " published by IBM J. Res. Develop., vol. 34, No. 1 Jan. 1990, pp. 59-70.

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