Fast-locking low-noise phase-locked loop

Details Fast-locking low-noise phase-locked loop Fast-locking low-noise phase-locked loop

1997-06-16

1998-10-13

Mottola, Steven

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331DIG2, 327159, 327160, H03L 708

Patent

active

058218173

ABSTRACT:
A phase-locked-loop device for generating an output signal of frequency Fo, n phase-lock with an input signal of frequency Fi, where Fo=N(Fi/M). The invention reduces noise and provides optimal-time frequency switching--settling in one cycle of the phase-detector reference signal by applying a signal shaped like a smooth broad hump to the voltage-controlled oscillator upon a frequency change command. It maintains optimal-time switching by keeping the PLL loop-gain constant. The invention reduces noise by eliminating the so called "dead-zone" in the digital phase-detector.

REFERENCES:
patent: 3983498 (1976-09-01), Malek
patent: 4827225 (1989-05-01), Lee

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