Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2010-10-11
2011-12-27
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000
Reexamination Certificate
active
08085074
ABSTRACT:
A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.
REFERENCES:
patent: 5608656 (1997-03-01), Purcell et al.
patent: 5630033 (1997-05-01), Purcell et al.
patent: 6122442 (2000-09-01), Purcell et al.
patent: 7502815 (2009-03-01), Drimer
patent: 7627806 (2009-12-01), Vijayaraghavan et al.
patent: 2005/0193045 (2005-09-01), Yamamoto et al.
patent: 2006/0133467 (2006-06-01), Clausen
patent: 2009/0028269 (2009-01-01), Pinkney
Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim and Soo-In Cho, “A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines”, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, Year May 2001, pp. 784-791.
“Chih-Kong Ken Yang”, Delay-Locked Loops-An Overview, Phase Locking in High Performance Systems , IEEE Press, Year 2003, pp. 13-22.
Chakravarty Sujoy
Janardhanan Jayawardan
Sreekiran Samala
Brady III Wade James
Donovan Lincoln
Houston Adam
Neerings Ronald O.
Telecky , Jr. Frederick J.
LandOfFree
Fast-locking delay locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast-locking delay locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast-locking delay locked loop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4300153