Fast lock/self-tuning VCO based PLL

Details Fast lock/self-tuning VCO based PLL Fast lock/self-tuning VCO based PLL

2000-09-18

2003-05-20

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S014000, C331S016000, C331S017000, C331S025000

Reexamination Certificate

active

06566966

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to Phase Lock Loop (PLL) circuits, and more particularly to PLL semiconductor integrated circuits having integrated voltage controlled oscillators (VCOs) such as those used in wireless communication systems.
BACKGROUND OF THE INVENTION
Phase Lock Loop (PLL) integrated circuits (ICs) find practical advantages in many electronic circuits, and in particular, in wireless communications systems dealing with high-speed data transfer including receivers. In wireless systems, it is critical to achieve both fast lock and perfect tuning of a voltage controlled oscillator (VCO) comprising a portion of the PLL. In conventional PLL circuits having an integrated VCO, tuning of the VCO may take a relatively long period of time which may not be tolerable in circuit designs handling high data transfer rates. The longer an oscillator takes to tune directly impacts the lock time of the PLL. Moreover, prior art semiconductor PLL circuits require a relatively large overhead circuit and extra power dissipation which are undesirable characteristics when embodied in silicon designs, such as in wideband code division multiple access (WCDMA) chipsets.
There is desired an improved PLL having both a fast lock time and an accurate self-tuning VCO having both a reduced overhead circuit and generating less power dissipation than those presently available.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a fast lock/self-tuning VCO based PLL whereby counters used in a divider are monitored to determine the lock condition of the PLL. A digital to analog converter (DAC) controls the course tuning of the VCO and is predistorted to lineraize the tuning of the VCO. Advantageously, the present invention merges the DAC with the VCO. The present invention allows an almost perfect tuning of the VCO and fast lock operation, which is critical in wireless systems handling high speed data transfer, such as WDCMA based communications. The present invention is preferably implemented in RFSiGe or CMOS process in a WDCMA chipset, and can be used in other systems such as GSM and EDGE. The present invention is also advantageous for use in new fractional-N PLL products.


REFERENCES:
patent: 3882403 (1975-05-01), Gerken
patent: 3982190 (1976-09-01), Schaefer
patent: 4550292 (1985-10-01), Smith
patent: 4859968 (1989-08-01), Gershon
patent: 5124671 (1992-06-01), Srivastava
patent: 5450621 (1995-09-01), Kianush et al.
patent: 5821818 (1998-10-01), Idei et al.
patent: 6035182 (2000-03-01), Shurboff

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