Boots – shoes – and leggings
Patent
1992-06-10
1993-03-09
Anderson, Lawrence E.
Boots, shoes, and leggings
364DIG1, 3642814, 3642817, 3642302, 395575, G06F 946
Patent
active
051931877
ABSTRACT:
A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.
REFERENCES:
patent: 3048332 (1962-09-01), Brooks et al.
patent: 3876987 (1975-04-01), Dalton et al.
patent: 4543630 (1985-09-01), Neches
patent: 4636942 (1987-01-01), Chen et al.
patent: 4718006 (1988-01-01), Nishida
patent: 4736319 (1988-04-01), Dasbuysta
patent: 4745545 (1988-05-01), Schiffleger
patent: 4754398 (1988-06-01), Pribnow
patent: 4796176 (1989-01-01), D'Amico et al.
patent: 4807116 (1989-02-01), Katzman et al.
patent: 4816990 (1989-03-01), Williams
patent: 4839800 (1989-06-01), Barlow et al.
patent: 4845722 (1989-07-01), Kent et al.
patent: 4891751 (1990-01-01), Call et al.
patent: 4901231 (1990-02-01), Bishop et al.
patent: 4905145 (1990-02-01), Sauber
patent: 4914570 (1990-04-01), Peacock
patent: 4920485 (1990-04-01), Vahidsafa
patent: 4937733 (1990-06-01), Gillett, Jr. et al.
patent: 4959781 (1990-09-01), Rubinstein et al.
patent: 5003466 (1991-03-01), Schan, Jr. et al.
patent: 5016162 (1991-05-01), Epstein et al.
patent: 5016167 (1991-05-01), Nguyen et al.
patent: 5062040 (1991-10-01), Bishop et al.
Gaertner Gregory G.
Miller Edward C.
Phelps Andrew E.
Schooler Anthony R.
Silbey Alexander A.
Anderson Lawrence E.
Supercomputer Systems Limited Partnership
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