Fast handling of branch delay slots on mispredicted branches

Details Fast handling of branch delay slots on mispredicted branches Fast handling of branch delay slots on mispredicted branches

1996-06-19

1998-07-21

Treat, William M.

395586, 39580023, G06F 938

Patent

active

057846030

ABSTRACT:
An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot instructions. When a mispredicted branch occurs, all instructions that follow the branch in execution order, including the branch delay slot instruction, die in the pipeline. The delay slot, if it is to be executed, is then reissued to the pipeline.

REFERENCES:
patent: 5509130 (1996-04-01), Trauloen et al.
patent: 5655097 (1997-08-01), Witt et al.
patent: 5706459 (1998-01-01), Atsushi
Su et al., "Branch with Masked Squashing in Superpipelined Processors", Proceedings of the 21st Annual International Sympsium on Computer Architecture, IEEE, Apr. 18-21, 1994, pp. 130-140.

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