Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1998-12-30
2004-02-24
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S308000
Reexamination Certificate
active
06697108
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
This application is related to CMOS imaging sensors.
Background: CMOS Imagers
For the past 20 years or so, the field of optical sensing has been dominated by the charged couple device (“CCD”). However, CCD sensors have a number of problems associated with their manufacture and use. CCD imagers require a special manufacturing process which is incompatible with standard CMOS processing. Thus CCD imagers cannot be integrated with other chips that provide necessary support functions, but require independent support chips to perform, for example, CCD control, A/D conversion, and signal processing. The operation of a CCD imager also requires multiple high voltage supplies varying from, e.g. 5V to 12V. The higher voltages produce higher power consumption for CCD devices. Consequently, costs for both the CCD image sensor and ultimately the system employing the sensor, remain high.
The recent advances in CMOS technology have opened the possibility of imagers offering significant improvements in functionality, power, and cost of, for example, digital video and still cameras. Advances in chip manufacturing processes and reductions in supply voltages have encouraged revisitation of CMOS technology for use in image sensors. The advent of sub-micron CMOS technology allows pixels which contain several FETs, and are circuits in their own right, to be comparable in size to those existing on commercial CCD imagers. Fabrication on standard CMOS process lines permits these imagers to be fully integrated with digital circuitry to create single-chip camera systems. A CMOS area array sensor (or CMOS imager) can be fabricated with other system functions, e.g. controller, A/D, signal processor, and DSP. Hence, the cost of the CMOS process is more economical than that of the CCD process. CMOS imagers can operate with a single low supply voltage (e.g. 3.3V or 5V). This provides lower power consumption than CCD imagers.
In CMOS area array sensors, each column (or row) has separate read circuitry. Driver mismatches between different columns produce column FPN. Much of the device mismatches are caused by the threshold voltage deviations between. CMOS transistors across the wafer.
Techniques such as Correlated Double Sampling (“CDS”), and Sequential Correlated Double Sampling (“SCDS”) can be used to suppress fixed pattern noise in CMOS imagers. In general, in a CDS architecture, a pixel sensing NMOS transistor performs double samplings. First the photo diode (“PD”) voltage signal is sensed, then a known, fixed voltage (for example, Vdd) is sensed. Subtraction is then performed to suppress the mismatch effect caused by pixel sensing NMOS transistor variations in a wafer.
For an on-chip integrated CDS system sensor array, the fixed pattern noise would be greatly reduced. But due to the additional sampling steps required for CDS, the sensor array requires additional clock signals for one pixel readout, and thus increases the length of time for readout of a whole array (or a frame) for a given clock speed. This results in a low frame rate and limits the capabilities of the sensor in live video application to approximately 30 frames per second.
Background: Fixed Pattern Noise
One significant disadvantage with CMOS imagers has previously limited their widespread application—Fixed Pattern Noise (“FPN”). FPN is a built-in characteristic of X-Y addressable devices and is particularly an issue with any sort of CMOS imaging chips. FPN is noise that appears in a fixed pattern because the noise level is related to the position of the pixel in the array, the geometry of the column bus, and the proximity of other noise sources. (In addition, there is purely random noise not correlated to the pixel position, but due to inherent characteristics of the detector.) The effect of FPN is like viewing a scene through a window made of photo negatives. FPN occurs when process limitations produce device mismatches and/or non-uniformities of the sensor during fabrication on a wafer. FPN consists of both pixel FPN and column FPN. Each pixel circuit comprises at least a photodiode and a sensing transistor (operating as source-follower) as shown in FIG.
3
. Mismatches of the sensing transistor between pixels may produce different output levels for a given input optical signal. The variations of these output levels is called pixel FPN. Additionally, each column (or row) has separate read circuitry. Driver mismatches between different columns (or rows) produce column FPN. Most device mismatches are caused by threshold voltage (V
T
) mismatches among CMOS transistors across the wafer.
A conventional solution for FPN suppression is to use a memory block to store the signal data for a whole frame and to subtract the FPN by sampling a reset voltage for the whole frame. The subtraction is done on a frame-by-frame basis which results in very slow frame rates.
Background: Correlated Double Sampling
Correlated double sampling plays an important role in removing several kinds of noise in high-performance imaging systems. Basically, two samples of the sensor output are taken. First, a reference sample is taken that includes background noise and noise derived from a device mismatch. A second sample is taken of the background noise, device mismatch, and the data signal. Subtracting the two samples removes any noise which is common (or correlated) to both, leaving only the data signal. CDS is discussed in greater detail in a paper by Chris Mangelsdorf, Analog Devices, Inc., 1996 IEEE International Solid-State Circuits Conference, which is hereby incorporated by reference.
Fast Frame Readout Architecture Using an Integrated CDS System
The present application discloses a high-speed pixel readout technique in a CMOS imager while minimizing low fixed pattern noise. The technique described in this patent disclosure can realize a fast frame readout rate for a sensor array with an on-chip integrated SCDS technique. The technique, together with a SCDS technique, enables one to achieve the CDS operation for a whole row of pixels simulta-neously. Pixels are then readout at the rate of one pixel per clock-cycle. Where prior-art systems utilize row and column decoders, or perhaps row and column shift registers for digital control readout, the disclosed innovative technique implements a one-hot-coded flip-flop architecture to simplify the digital control readout.
An advantage of the disclosed innovative technique and structure is that fewer clock cycles are required to read out the pixels. After an initial read-preparation phase of no more than four clock cycles, each pixel of a row requires only one additional clock cycle to be readout. Another advantage is that there is a significant savings in chip real estate associated with the high-speed readout advantages afforded with the innovative technique and structures. Another advantage of the disclosed innovative technique and structures is that faster frame rates are possible.
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Mangelsdorf et al., “A CMOS Front-End for CCD Cameras,” Session 11/Electronic Imaging Circuits/Paper FA 11.5, p. 186, pp. 189-191.
Blanksby et al., “Noise Performance of a Color CMOS Photogate Image Sensor,” IDEM '97, pp. 205-208.
Chen Zhiliang Julian
Dierschke Eugene G.
Brady III W. James
Garber Wendy R.
Moore J. Dennis
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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