Fast frame buffer system architecture for video display system

Details Fast frame buffer system architecture for video display system Fast frame buffer system architecture for video display system

1997-06-30

2000-02-01

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345203, G09G 536

Patent

active

060209011

ABSTRACT:
A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.

REFERENCES:
patent: 5442379 (1995-08-01), Bruce et al.
patent: 5544306 (1996-08-01), Deering et al.
patent: 5617367 (1997-04-01), Holland et al.
patent: 5696534 (1997-12-01), Lavelle et al.
patent: 5745125 (1998-04-01), Deering et al.
Computer Graphics Proceedings, Annual Conference Series, "FBRAM: A New Form of Memory Optimized for 3D Graphics" pp. 167-174 by Deering et al, Jul. 1994.
IEEE Custom Intergrated Circuits Conference, "A 66 MHz DSP-Augmented RAMDAC for Smooth-Shaded Graphic Application" by Harston et al, pp. 15.5.1-15.5.4,May 1991.

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