Fast fourier transforming apparatus and method, variable bit rev

Details Fast fourier transforming apparatus and method, variable bit rev Fast fourier transforming apparatus and method, variable bit rev

1998-01-21

2000-09-05

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 1500

Patent

active

061157287

ABSTRACT:
In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

REFERENCES:
patent: 5491652 (1996-02-01), Luo et al.
E. Bidet, et al., "A Fast Single Chip Implementation of 8192 Complex Points FFT", Proc. of IEEE 1994 Custom Integrated Circuits Conference, pp. 207-210, 1994.
A. Delaruelle, et al., "A Channel Demodulator IC for Digital Audio Broadcasting", Proc. of IEEE 1994 Custom Integrated Circuits Conference, pp. 47-50, 1994.

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