Fast fourier transform architecture using hybrid n-bit-serial ar

Details Fast fourier transform architecture using hybrid n-bit-serial ar Fast fourier transform architecture using hybrid n-bit-serial ar

1987-09-14

1989-09-19

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 15332

Patent

active

048687766

ABSTRACT:
A fast Fourier transform circuit, including an illustrative radix-eight discrete Fourier transform (DFT) kernel that operates on an n-bit-serial data format, for an efficient serial-like, pipelined operation within the DFT. The circuit performs a four-point DFT on half of the input data words at a time, stores intermediate results from the four-point DFT in a commutation stage, then combines the intermediate results in two two-point DFTs. Internal multiplication in the eight-point DFT is effected in delay registers that also serve to store the intermediate results, thereby providing an economy of timing and circuit routing. Interleaving and deinterleaving operations convert the data format between three-bit-serial and conventional bit-parallel used outside the eight-point DFT kernel, which may therefore be easily cascaded for more complex FFT operations. The DFT kernel also includes means for selectively bypassing butterfly computation modules to perform shorter-length DFTs.

REFERENCES:
patent: 4275452 (1981-06-01), White
patent: 4282579 (1981-08-01), Speiser et al.
patent: 4298950 (1981-11-01), Smith, Jr.
patent: 4547862 (1985-10-01), McIver et al.
patent: 4602350 (1986-07-01), Gray
H. L. Groginsky & G. A. Works, "A Pipeline Fast Fourier Transform, " IEEE Trans. on Computers, vol. C-19, No. 11, pp. 1015-1019, 1970.

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