Fast Fourier transform address generator

Details Fast Fourier transform address generator Fast Fourier transform address generator

1994-10-21

1996-02-13

Mai, Tan V.

Boots, shoes, and leggings

G06F 1500

Patent

active

054916526

ABSTRACT:
A for Fast Fourier Transform (FFT) address generator utilizes a butterfly counter to count a butterfly count for each butterfly stage of FFT in numerical sequence; and a stage counter to count a stage count for the butterfly stage of FFT in bit-shifting manner. A data address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a data address according to a first regularized logic function. A twiddle factor address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a twiddle factor address according to a second regularized logic function.

REFERENCES:
patent: 4393457 (1983-07-01), New
patent: 5233551 (1993-08-01), White
patent: 5365469 (1994-11-01), Mercy

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