Fast flush load of LSSD SRL chains

Details Fast flush load of LSSD SRL chains Fast flush load of LSSD SRL chains

1995-12-08

1997-06-17

Beausoliel, Jr., Robert W.

Excavating

371 221, 371 251, G01R 3128

Patent

active

056404026

ABSTRACT:
A method of effectively reducing a length of shift register (SR) latches used in scan design testing for testing macro structures embedded within very large logic structures eliminates tester hardware buffer limitations required to load and unload a long chain SR. A plurality of shift register latches are connectable in a chain for scan design testing. Each shift register latch is composed of an L1 and an L2 latch receiving A and B clocks, respectively, to shift data into and out of the shift register latch. First specific shift register latches in a chain of shift register latches are used to generate test data inputs to an embedded macro structure, second specific shift register latches in the chain of shift register latches are used to receive test data outputs from the embedded macro structure. A separate B' clock is applied to the L2 latches of the first and second specific shift register latches while maintaining the B clock for the L2 latches for other shift register latches in the chain. The B' clock is similar to the B clock but displaced in time. The chain of shift register latches is flushed prior to a load operation of data for testing the embedded macro structure by simultaneously pulsing the A and B clocks. Then the embedded macro structure is loaded from the L2 latches of the first specific shift register latches with the L1 latches of the second specific shift register latches being loaded from the embedded macro structure by pulsing the B' clock to produce a scan cycle for the embedded macro structure.

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