Fast FiFo memory storage system

Details Fast FiFo memory storage system Fast FiFo memory storage system

2000-08-30

2002-04-02

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Addressing

Sequential

C365S189020, C365S230050

Reexamination Certificate

active

06366529

ABSTRACT:

RELATED PATENT APPLICATIONS
This application is related to U.S. Patent Application entitled Fast Reprogrammable FIFO Status Flags System, Ser. No. 09,634,449, filed on Aug. 8, 2000, by Kenneth L. Williams and Rakesh N. Joshi.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to FIFO memories, and more particularly to a fast FIFO memory storage system implemented substantially from traditional sequential memory elements.
2. Description of the Prior Art
Recent advancements in technology continue to provide data processing and communication devices that transmit and process data at ever increasing speeds. In order to accommodate these increased data transmission and data processing speeds, there is now a need to provide even faster FIFO memory storage systems. Such memory storage system should be capable of supporting write and read operations at far faster rates and with far shorter data access times than possible with the fastest available compiled static random access memories (RAM)s.
U.S. Pat. No. 5,255,242, entitled Sequential Memory, issued Oct. 19, 1993 to Ward, et al., and assigned to the assignee of the present invention, discloses a sequential memory using interleaved memories with associated output buffers to accomplish high data rates. U.S. Pat. No. 5,255,242 is incorporated by reference herein in its entirety. The technique disclosed by the '242 patent uses data access control circuitry and bank select circuitry to control the order in which the memory banks are written to and read from. The technique disclosed by the '242 patent further uses output buffer circuits allowing a data word to be read instantaneously after it has been written to the sequential memory. Although the invention disclosed and claimed by Ward et al. in the '242 patent combines slower sequential memory units to obtain a faster sequential memory system, that system operates at about only twice the operating frequency of the separate memory units. The invention of Ward et al. allows several read clock cycles before requiring data to appear on the outputs, so the data access time does not need to be as short as required to support the above discussed increased data transmission and processing speeds.
In view of the foregoing, there is a need for a fast FIFO memory storage system capable of operation at nearly three times the write and read frequencies of currently available RAMs. Such a system should preferably include a sufficiently fast cache system to temporarily store data in situations where the required data access time is shorter than that achievable using currently available RAMs. The FIFO memory storage system should preferably be designed in ASIC standard cell design flow using off-the-shelf gate and memory modules manufactured via a well-known, long-standing, inexpensive process to achieve high speed operation with very high reliability, least cost, and shorter design cycle times than that achievable using custom circuitry.
SUMMARY OF THE INVENTION
The present invention is directed to a fast FIFO memory data storage system that is implemented using slower memory storage elements that by themselves are not capable of operation at data processing speeds achievable with the fast FIFO memory data storage system. According to one embodiment, the system includes four RAM blocks, a write ring-counter, a read ring-counter, a plurality of write and read enabling gates, a one-of-four data selector, a data output select multiplexer (mux), and an output register.
The write ring-counter generates four write-select signals (WS
0
-WS
3
). Upon a low level system reset, WS
0
is preset to high, and WS
1
-WS
3
to low. If reset is high, a primary write enable is high, and there is a low-to-high transition of the write clock. This advances the write ring-counter to the next state where WS
1
is high and WS
0
-WS
3
are low. At any time, only one of the write-select signals is high. At the same time, if the primary write-enable is high, then a secondary write-enable signal corresponding to the currently high write-select signal will be high. When one of the secondary write-enable signals is high when the write clock goes high, the data word on the input data bus gets written into the corresponding RAM block.
The read ring-counter functions in the same manner as the write ring-counter. A read-select signal (RS
0
-RS
3
) selects which RAM block output word to send to the output register. If a primary read-select signal is high and the read clock goes from low-to-high, the selected output word is clocked into the output register, a new output word is read from the selected RAM block, and the read ring-counter advances to the next state. Upon a low level on the system reset, all of the bits in the output register are cleared.
Each RAM block includes a small FIFO memory element to accommodate processing of output data from the RAM block at certain times when the written data must be available at the RAM block output even before sufficient time for a RAM read has elapsed. Data on the data input bus is written to the small FIFO on a rising edge of the write clock while the primary write-enable is high. Data written to the small FIFO is available to be read out much faster than RAM data. According to one embodiment, the small FIFO capacity is four words. Therefore, once four words have been written, the small FIFO is full and additional write attempts are ignored until one or more words have been read out of the small FIFO. New data is read out of the small FIFO on a rising edge of its read clock while the primary FIFO read-enable is high. When the small FIFO is empty, the first word written automatically appears on the small FIFO output. The small FIFO also stores (in parallel with the data word) the write address associated with the data word for use in arbitrating whether RAM or small FIFO data are sent to the RAM block output. The system reset, when taken low, also resets the small FIFO to its empty state.
In one aspect of the invention, a fast FIFO memory storage system is implemented using slower memory storage units.
In yet another aspect of the invention, a fast FIFO memory storage system is implemented in which writes and reads can occur at far faster rates and with far shorter data access times than possible with the fastest available compiled static RAMs.
In still another aspect of the invention a fast FIFO memory storage system is implemented to provide a memory system capable of operating at nearly three times the write and read frequencies of presently available RAMs.
Another aspect of the invention is associated with providing a fast FIFO memory storage system in accordance with ASIC standard cell design flow using off-the-shelf gate and memory modules built in an older, less-expensive process to accommodate high speed operation with very high reliability, minimal cost, and very short design cycle times when compared with present design practices.


REFERENCES:
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5027326 (1991-06-01), Jones
patent: 5255242 (1993-10-01), Ward et al.
patent: 5473756 (1995-12-01), Traylor
patent: 6072781 (2000-06-01), Feeney et al.

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