Fast electrical complete turn-off optical device

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With light activation

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Details

257115, 257463, 257464, H01L 2974, H01L 31111

Patent

active

056524390

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The invention relates generally to optoelectronic pnpn devices and more particularly to a layer structure suitable for fast electrical complete turn-off of such devices and to a method for efficient and fast operation of such devices and differential pairs of such devices.


BACKGROUND

Optical devices concerned with this invention are those including three junctions, e.g. optical thyristors and Shockley diodes. Such devices are promising candidates for use in fast and sensitive optical receivers and combined optical transmitter-receivers for digital signals in fiber and free-space optical interconnections.
For use in industrial applications, however, the existing trade-off between cycle frequency and optical sensitivity is a major problem. The cycle frequency corresponds with the bitrate for reception (and eventual digital optical retransmission). A measure for the optical sensitivity is the required energy of optical input pulses to obtain reliable detection.
A high optical sensitivity can be reached by biasing the pnpn-device critically close to the breakover voltage. To reach this point, the bias has to be applied slowly (at least in microseconds) in order to avoid dV/dt triggering. Furthermore, the turn-on delay after application of a light pulse is also too long, namely micro- or milliseconds.
JP-A-3-235926 teaches that a high optical sensitivity can be obtained without critical biasing by using a differential pair of pnpn-devices instead of a single one. However, the trade-off between optical sensitivity and cycle speed remains a concern. Before an input light pulse is applied, the number of free carriers in both pnpn devices of the pair have to be equal. High sensitivity for input light requires a long waiting time before the optical light is applied to ensure the balance. It has been shown experimentally that a higher cycle speed results in a lower sensitivity.
High cycle speed has been obtained (without high optical sensitivity) by extracting carriers using a third and a fourth contact on the center layers of a pnpn device (Y. Tashiro, K. Kasahara, N. Hamao, M. Sugimoto, R. Yanase, "High speed response in optoelectronic gated thyristor", Japanese J. Appl. Phys., vol 26, 1014 (1987) and also G. W. Taylor, R. S. Mand, J. G. Simmons, and A. Y. Cho, "Ledistor, a three terminal double heterostructure optoelectronic switch.", Appl. Phys. Lett. vol 50, 338 (1987). However, not all majority carriers can be extracted since the extracting layer itself gets punched through.
Fast extraction of free carriers in the center n-layer has already been obtained in a double heterojunction optical thyristor by applying a negative voltage to the anode (P. Heremans, M. Kuijk, D. A. Suda, R. Vounckx, R. E. Hayes and G. Borghs, "Fast Turn-Off of Two-Terminal Double Heterojunction Thyristor Device" Appl. Phys. Lett. 61, 1326 (1992). A turn-off time of 10 ns and an optical sensitivity of up to 100 pJ have been reported. This optical input energy is large due to the fact that an uncontrollable residue of free holes remains in the center p-layer of the structure. This uncertainty in the remaining free holes results in higher light input being required to switch the device.


SUMMARY OF THE INVENTION

It is the object of the invention to provide an optical device in which both center layers can be completely depleted, thereby resulting in the aforementioned trade-off being avoided.
This objective is attained in accordance with the invention with an optoelectronic device including at least a first, a second, a third and a fourth layer, said first and third layers being of one conductivity type while said second and fourth layers are of the opposite conductivity type, the said second and third layers complying with the following relation: ##EQU1## and either one of said second and third layers complying with the following relation: ##EQU2## where: W is the physical width of the layer (in cm),
By applying a negative voltage pulse to the anode with respect to the cathode, complete carrier removal from the

REFERENCES:
patent: 4166224 (1979-08-01), Hutson
patent: 4244000 (1981-01-01), Ueda et al.
patent: 4999688 (1991-03-01), Hara et al.
patent: 5136353 (1992-08-01), Pankove et al.
patent: 5148253 (1992-09-01), Kimura
Applied Physics Letters, vol. 61, No. 11, Sep. 1992, pp. 1326-1328.
Applied Physics Letters, vol. 57, No. 11, Sep. 1990, pp. 1075-1077.
Microelectronic Engineering, vol. 19, No. 9, Sep. 1992, pp. 49-52.
International Electron Devices Meeting, Dec. 1991, pp. 433-436.
IEEE Transactions on Electron Devices, vol. 39, No. 8, Aug. 1992, pp. 1858-1864.
Electronics Letters, vol. 26, No. 5, Mar. 1990, pp. 280-282.

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