Fast edge triggered self-resetting CMOS receiver with parallel L

Details Fast edge triggered self-resetting CMOS receiver with parallel L Fast edge triggered self-resetting CMOS receiver with parallel L

1994-06-10

1995-11-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 52, 327 57, 327202, 327203, 36518905, H03K 5153

Patent

active

054650607

ABSTRACT:
A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/compliment generator circuit (TCG) for generating a data and its compliment from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

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Chappell, Terry I.; Chappell, Barbara A.; Schuster, Stanley E.; Allan, James W. Klepner, Stephen P.; Joshi, Rajiv V.; and Franch, Robert L. "A 2-ns Cycle, 3.8ns Access 512-kb CMOS ECLS SRAM with a Fully Pipelined Architecture," IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991.

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