Fast differential sample-and-hold circuit

Details Fast differential sample-and-hold circuit Fast differential sample-and-hold circuit

1996-09-16

1998-07-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

G11C 2702

Patent

active

057867127

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The invention relates to circuits for sampling and holding analog electrical signals, and more particularly fast sample-and-hold circuits.
Such sample-and-hold circuits are used, for example, in the processing of the signals output by CCD photosensitive detectors.
More generally, the invention also relates to the sample-and-hold circuits used in any other type of application.
2. Discussion of the Background
The production of fast sample-and-hold circuits essentially involves the use of open-look architectures, so as to best exploit the intrinsic characteristics of the technologies used. Such is the case, for example, with the fast NPN bipolar transistor technology.
According to the prior art, as described, for example, in patent EP-A-0,394,506, examples of known fast sample-and-hold circuits include architectures such as that represented in FIG. 1. This is a differential-type structure in which the NPN transistors T1 and T2 act as switches.
The input signals are applied to the bases B1 and B2 of the respective transistors T1 and T2, and the output signal is recovered between the emitters E1 and E2 of the transistors T1 and T2.
A capacitor C12 connects the emitters E1 and E2. The circuit represented in FIG. 1 operates in two regimes. One of the regimes is the follower regime. Each of the two transistors T1 and T2, biased using a current generator Io connecting its emitter to the earth of the circuit, is then on. The other regime is the off regime. The current sources Io are then coupled and the transistors T1 and T2 are off.
In follower regime, if the common-mode bias voltage present on each of the bases B1 and B2 is denoted Vm, the variable input signal applied to the base B1 is denoted ##EQU1## and the variable input signal applied to the base B2 denoted ##EQU2## the total voltage VB1 applied to the base B1 is written: ##EQU3## and the total voltage of VB2 applied to the base B2: ##EQU4##
The memory capacitor C12 of the sample-and-hold circuit connects the emitters E1 and E2.
The voltage VC12 existing across the terminals of this capacitor is therefore written emitters E1 and E2.
Now, it is known that: transistors T1 and T2.
The voltage of VC12 can therefore be written:
In the so-called "small signal" regime, that is to say when the amplitude of the variable input signal is very small compared to the amplitude of the DC bias voltages, it is known to the person skilled in the art that the term VBE2-VBE1 can be neglected. However, when the amplitude of the variable input signal can no longer be considered as small compared to the amplitude of the DC voltages, this term is no longer negligible.
The circuit is then termed nonlinear.
In practice, three causes give rise to this nonlinearity.
A first cause is the Early effect, which appears in the transistors T1 and T2. The voltage VBE of each transistor then varies under the effect of the modulation of the saturation current of the baseemitter junction of the transistor. This first cause of nonlinearity is solved by producing a connection layout known to the person skilled in the art by the name "cascode" connection. As represented in FIG. 1, transistors TC1 and TC2, suitably biased by the voltages Vo applied to their base, are then connected in series with the respective transistors T1 and T2.
A second cause resides in the fact that the transistors T1 and T2 do not operate with a constant current but with a dynamic current modulated by the current Ic flowing from the capacitor C12. As is known to the person skilled in the art, this gives: ##EQU5## where Ut is the thermodynamic potential (Ut=26 millivolts at a temperature chosen to represent the natural logarithm of the quantity X.
A third cause is due to the combination of the first and second causes, which combine and make the base currents of T1 and T2 nonlinearly variable (modulation of the base current by modulation of Ic, modulation of the gain of the transistor by the Early effect).
According to the prior art, the second cause is attenuated by increa

REFERENCES:
patent: 4873457 (1989-10-01), Sanielevici
patent: 5039880 (1991-08-01), Astegher et al.
patent: 5047666 (1991-09-01), Astegher et al.
patent: 5081423 (1992-01-01), Koyama et al.
patent: 5298801 (1994-03-01), Vorenkamp

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