Fast data synchronizer

Details Fast data synchronizer Fast data synchronizer

1985-12-18

1988-05-31

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

047485884

ABSTRACT:
A circuit arrangement for synchronizing source data from a source system with a clock and/or clocks from a sink system. The circuit arrangement includes a source counter, a buffer, a sink counter and a controller. The source data is placed in consecutive buffer positions under the control of the source counter. The sink counter is made to "follow" the source counter and identifies the location in the buffer whereat output data is to be extracted. The controller monitors the counters and generates control signals representative of the state of the buffer.

REFERENCES:
patent: 3188569 (1965-06-01), Mahony et al.
patent: 4021784 (1977-05-01), Kimlinger
patent: 4027292 (1977-05-01), Okamoto et al.
patent: 4054747 (1977-10-01), Pachynski
patent: 4056851 (1977-11-01), Hovagimyan et al.
patent: 4258418 (1981-05-01), Heath
Patent Abstracts of Japan, vol. 6, No. 151 (E-124) (1029), Aug. 11th, 1982; & JP-A-57 75 046 (Fujitsu K.K.) 11-05-1982.

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