Fast cycle time-low latency dynamic random access memories and s

Details Fast cycle time-low latency dynamic random access memories and s Fast cycle time-low latency dynamic random access memories and s

1996-01-11

1997-06-03

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365203, 365207, G11C 700, G11C 702, G11C 800

Patent

active

056361742

ABSTRACT:
A memory 200 comprising a plurality of rows and columns of memory cells, each column of cells associated with a conductive bitline 301. Memory 200 further includes precharge circuitry 204, 206 for precharging a selected one of the bitlines in response to a received control bit.

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patent: 5430676 (1995-07-01), Ware et al.
patent: 5434817 (1995-07-01), Ware et al.
patent: 5493535 (1996-02-01), Cho
patent: 5495444 (1996-02-01), Okubo et al.
patent: 5528552 (1996-06-01), Kamisaki

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