Fast cycle time clocked amplifier

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307451, 36518907, 365204, 365205, H03F 345, H03K 19094

Patent

active

050897268

ABSTRACT:
A circuit incorporating a clocked first stage and unlocked second and third stages with amplification for driving capacitance loads with the output nodes each coupling its changed state back to the earlier stages to reset them independent of the clock. The circuit may use complementary metal-oxide semiconductor devices of various gate widths.

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patent: 4845677 (1989-07-01), Chappell et al.
B. A. Chappell et al., CMOS Preamplifier/Clocked Amplifier For ECL Conversion, IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988, p. 280.
F. Towler et al., "A 128k 6.5ns Access/5ns Cycle CMOS ECL Static RAM", 1989, IEEE International Solid-State Circuits Conference Digest of Tech. Papers.
S. H. Dhong et al., High Density Memory Cell Structure With Two Access Transistors, IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988, p. 409.

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