Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2003-02-18
2004-09-21
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S190000, C365S189050, C365S230060
Reexamination Certificate
active
06795370
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-353172, filed Dec. 13, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and more particularly to a fast cycle synchronous DRAM (SDR-FCRAM) having a function of rapidly reading/writing random data from or into a memory cell array and a data write system of a double data rate synchronous DRAM (DDR-FCRAM) for realizing the data transfer rate twice that of the above DRAM.
In order to enhance the data access speed of the DRAM to that of an SDRAM and attain a large data band width (the number of data bytes for each unit time) by use of a high clock frequency (tCK), a synchronous DRAM (SDRAM) is invented and is already put into practice from the 4-Mbit or 16-Mbit DRAM generation. In the present 64-Mbit generation, the SDARM occupies a large part of the amount of all of the DRAMs used.
Recently, in order to further enhance the operation speed of the SDRAM, a double data rate SDRAM which is operated at the data transfer rate twice that of the conventional case by operating the same in synchronism with both of the leading edge and trailing edge of a clock signal is proposed and actively commercialized.
In order to enhance the data transfer rate in the SDRAM, the data bandwidth is actively increased, but it is difficult to make random access to cell data in a memory core, that is, to enhance the speed of data access to a row address which has been changed to indicate a different row. This is because the cycle time (random cycle time=tRC) of the memory core cannot be greatly reduced since a certain period of time (which is referred to as core latency) is required for the destructive readout and amplifying operation inherent to the DRAM and the precharge operation prior to the next access to the memory core in the SDRAM.
In order to solve the above problem, a so-called fast cycle RAM (FCRAM) in which access to the memory core and the precharge operation thereof are pipelined to reduce the random cycle time of the conventional DRAM to half or less is proposed and will be started to be commercialized mainly in the network field in which random data of a router or LAN switch using SRAMs in the prior art is transferred at high speed.
The basic system of the data readout operation of the FCRAM is described in International Application (International Publication Number WO98/56004 (Fujioka et al.) using Jpn. Pat. Appln. Nos. 09-145406, 09-215047 and 09-332739 as the basic application, for example.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: means for latching data to be written into the memory cell; and means for driving a data line pair according to write data latched in the means for latching data, wherein writing of data fetched from the exterior in response to input of a command is started when a next command is set.
According another aspect of the present invention, there is provided a data write method for a fast cycle random access memory comprising the steps of: supplying serial data input to a data pin from the exterior to a data input buffer, converting the serial data into parallel data in a serial/parallel converting circuit and them transferring the parallel data to an input data register provided adjacent to a DQ write driver via a write data line; and writing data, which is latched in the input data register in a preceding write cycle, into a memory cell via the DQ write driver, a data line pair, an I/O gate and a bit line pair when data is written into the memory cell in a next write cycle.
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Abe Katsumi
Ohshima Shigeo
Ohtake Hiroyuki
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Nguyen Tuan T.
Nguyen Van Thu
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