Fast cycle RAM and data readout method therefor

Details Fast cycle RAM and data readout method therefor Fast cycle RAM and data readout method therefor

2002-06-04

2003-02-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S063000, C365S189080, C365S230060

Reexamination Certificate

active

06522600

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and a data readout method therefor and more particularly to a fast cycle synchronous DRAM (SDR-FCRAM) having a function of rapidly reading/writing random data from or into a memory cell array in synchronism with a clock signal and a data readout method for a double data rate synchronous DRAM (DDR-FCRAM) for realizing the data transfer rate twice that of the above DRAM.
In order to enhance the data access speed of a DRAM to that of an SDRAM and attain a large data band width (the number of data bytes for each unit time) by use of a high clock frequency (cycle time tCK), a synchronous DRAM (SDRAM) is invented and is already put into practice from the 4-Mbit or 16-Mbit DRAM generation.
Recently, in order to further enhance the operation speed of the SDRAM, a double data rate SDRAM which is operated at the data transfer rate twice that of the conventional SDRAM by operating the same in synchronism with both of the rise edge and fall edge of a clock signal is proposed and actively commercialized.
In order to enhance the data transfer rate, the data bandwidth is actively increased, but it is difficult to enhance the speed of random access to cell data in a memory core, that is, the sped of data access to a row address which has been changed to indicate a different row. This is because the cycle time (random cycle time=tRC) of the memory core cannot be greatly reduced since a certain period of time (which is referred to as core latency) is required for the destructive readout and amplifying operation inherent to the DRAM and the precharge operation prior to the next access to the memory core.
In order to solve the above problem, a so-called fast cycle RAM (FCRAM) in which access to the memory core and the precharge operation thereof are pipelined to reduce the random cycle time to half of that of the conventional DRAM or less is proposed and will be started to be commercialized mainly in the network field in which random data of a router or LAN switch using SRAMs in the prior art is transferred at high speed.
The basic system of the data readout operation of the FCRAM is described in International Application (International Publication Number W098/56004 (Fujioka et al.)) based on Jpn. Pat. Appln. Nos. H09-145406, H09-215047 and H09-332739 used as the basic application, for example.
This invention is to improve the data readout operation of the FCRAM defined in the above International Application and relates to the improvement of a method for supplying a row access instruction and column access instruction.
First, the basic system and the operation of data readout in the FCRAM disclosed in the above International Application are briefly explained with reference to
FIGS. 1
to
5
.
FIGS. 1
to
3
correspond to FIGS. 4 to 6 in International Publication No. W098/56004.
FIG. 1
is a principle diagram for reducing or shortening the random cycle time tRC in the FCRAM and shows a row-series pipeline operation.
FIG. 2
is a detail timing chart of an internal operation for realizing the pipeline operation.
FIG. 3
is a timing chart for illustrating the operation for enhancing the row access speed by the self-precharge operation.
FIG. 4
shows an example of a command input method at the readout time defined in the FCRAM.
FIG. 5
is a command status diagram in the data readout system described in the above International Application.
In
FIGS. 2 and 3
, WL indicates the potential of a word line, BL, {overscore (BL)} indicate the potentials of paired bit lines, SAE indicates an enable signal of a bit line sense amplifier, CSL indicates a signal (which is the potential of the column selection line) selected according to a column address, for transferring data on the bit line pair BL, {overscore (BL)} amplified by the bit line sense amplifier to a peripheral data bus, EQL is a precharge/equalizing signal for the paired bit lines, ACT indicates a row access command and RD is a column access command.
In
FIG. 4
, BA
0
to BA
3
indicate a bank address, A
0
to A
10
indicate an address, UA indicates an upper address, LA
0
to LA
9
indicate a lower address, and LA
1
, LA
0
among the lower address LA
0
to LA
9
indicate a burst address.
In
FIG. 5
, DESL indicates a deselect operation, POWER DOWN indicates a power down operation, MODE REGISTER indicates a mode register, WRITE indicates a write operation, IDLE indicates a 50% adder latched, READ indicates a read operation, AUTO-REFRESH indicates an auto-refresh operation, SELF-REFRESH indicates a self-refresh operation, PDEN indicates a power down command, PDEX indicates a power down release command, MRS indicates a mode register set command, ACT indicates a row access command (first command), RD indicates a read column access command (second command), REF indicates a auto refresh command, WR indicates a write access command, SELF indicates a self-refresh command and SELFX indicates a self-refresh release command.
In order to enhance the speed of random data readout from a memory cell array, it is considered that the following three stages are pipelined as shown in FIG.
1
:
(1) command decoding operation and peripheral circuit operation;
(2) sense amplification operation; and
(3) data output operation.
In this case, in the DRAM, the longest time is required for the stage (2), that is, for “word line selection cycle”+“sense amplifier driving cycle”+“reset cycle (sense amplification cycle)” as shown in the timing chart of FIG.
2
. In order to reduce the time to minimum, instead of decoding the row address, subjecting data read out from the memory cell MC connected to the selected word line WL to the differential amplification by the bit line sense amplifier S/A, terminating the restore operation, and then successively opening the column selection gates in response to a plurality of column addresses by use of the column selection lines CSL to make burst access as in the conventional SDRAM, it is necessary to read out data of a necessary burst length to the bit line sense amplifier S/A so as to instantly terminate the sense amplifying operation (stage (2)) by simultaneously opening a plurality of column selection gates larger in number than the SDRAMs after the restore operation is terminated and then effect the reset (precharge) cycle in the shortest time while the data outputting operation (stage (3)) is being effected.
In order to realize the above operation, the operation based on the timing chart shown in
FIG. 3
is required. The feature of the operation shown in
FIG. 3
is that a row access command ATC and column access command RD (in this case, it indicates “read”) are supplied to the FCRAM as one packet. The commands are supplied in response to successive clock input pulses so that the command interval will become minimum and the command cycle time can be reduced. By fetching the row access command ACT and column access command RD in synchronism with the two successive clocks, it becomes possible to fetch a column address CAi which is fetched at the same time as the column access command RD at earlier timing, thereby making it possible to select a column selection line CSL at earlier timing. Further, as a secondary effect, part of the column address CAi can be used as an address for dividing the sense amplifiers, and therefore, the number of sense amplifiers to be operated is limited in comparison with the conventional DRAM and the operation speed of the stage (2) can be enhanced.
AS shown in
FIG. 5
, in the above readout method, a row address is latched in response to input of a first command ACT in the deselect state (standby state) to start the operation of the row-series peripheral circuit. Next, part of the column address CAi is used as a row address for decoding the sense amplifier by use of the second command RD (column access command for “read”) or {overscore (WR)} (column access command for “write”) and access to the thus limited memory core is started. Then, after termination of the access, the deselect state is automatically

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