Fast control for round unit

Details Fast control for round unit Fast control for round unit

1991-09-20

1993-09-14

Nguyen, Long T.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

052455637

ABSTRACT:
A method and processor for evaluating numbers processes components of a pair of input numbers A, B in a plurality of identical gate structures. Each gate structure receives information from two bit positions and operates without carry information or any earlier computations to produce a conditional sum word. A control signal derived from the conditional sum word provides the same evaluation as the actual sum in fewer processing steps. A preferred embodiment produces the sticky bit for a rounding off unit in a floating point processor.

REFERENCES:
patent: 4589084 (1986-05-01), Fling et al.
patent: 4589087 (1986-05-01), Auslander et al.
patent: 4924422 (1990-05-01), Vassiliadis et al.
patent: 5020016 (1991-05-01), Nakano et al.
patent: 5055999 (1991-10-01), Frank et al.
patent: 5119481 (1992-06-01), Frank et al.
Mark R. Santoro et al., "Rounding Algorithms For IEEE Multipliers", Stanford University.

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