Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-12-17
2001-10-09
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06300769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital electronic devices, and in particular to a fast method and circuit for comparing two words and suitable for use in built-in self-test and built-in self-repair modules.
2. Description of the Related Art
Since users generally depend upon the reliability of memory chips and other integrated circuits for their own systems to function properly, it is common practice for the chip manufacturers to test the functionality of chips at the manufacturing site before the chips are sold to users. The manufacturers' reputations depend upon the reliability of their chips. As the line width within an integrated circuit chip continues to shrink, this reliability becomes more difficult to achieve. An ongoing challenge for the chip manufacturers is to increase the number and density of transistors on a chip without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
Before the chips are released for shipment, they typically undergo testing to verify that the circuitry for each of the major on-chip modules is functioning properly. One standard way for testing chips involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive in terms of time requirements and equipment costs.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units are now commonly incorporated into memory chips and other integrated circuits. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
A memory BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a memory BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the memory BIST unit is able to determine whether the memory cell is faulty. If too many errors are detected, then the fault may exist in the support circuitry for the memory cell array.
It is not uncommon for a significant percentage of the memory cells within a memory chip to fail because of defects in the substrate or errors in the manufacturing process. To compensate for this, many memory chips are provided with a set of extra memory cells that can be used in place of the defective ones. Configuring the memory chip to replace the defective cells is termed “Repairing” the memory array. Some memory repair is performed at the manufacturing site. Conventional repairing techniques bypass the defective cells using fuseable links that cause address redirection. However, these techniques require significant capital investment for implementing the repairing process, and moreover they fail to address the possibility of failure after shipment from the manufacturing facility.
To reduce repair costs and allow field repairs, some memory chips have been equipped with built-in self test (BIST) and built-in self repair (BISR) circuitry. The BIST circuit detects faults in the memory array and notifies the BISR circuit of the fault locations. The BISR circuitry generally reassigns the row or column containing the failing cell to a spare row or column in the memory array. BIST and BISR are typically performed each time power is applied to the system. This allows any latent failures that occur between subsequent system power-ups to be detected in the field.
Unfortunately, providing BIST and BISR for a memory chips lengthens the required pause time between power-on and the first usage of the memory chip. Furthermore, usage of a BISR unit limits the memory access speed by adding to the memory access times. Consequently, it is desirable to increase the speed of BIST and BISR circuitry in an inexpensive manner.
SUMMARY OF THE INVENTION
Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted. A first clock transistor may be coupled between the first node and a second node and configured to conduct when a clock signal is asserted, and a second clock transistor may be coupled between a positive source voltage and the second node and configured to conduct when the clock signal is de-asserted. If a pull-up resistance is provided, this allows the first or second node to indicate the match or mismatch of the input words. Further robustness may be provided by a Schmitt-trigger configuration coupled to the second node.
REFERENCES:
patent: 5471188 (1995-11-01), Chappell et al.
patent: 5684849 (1997-11-01), Ueno
patent: 6057709 (2000-05-01), Hesley
Leroux E P
LSI Logic Corporation
Metjahic Safet
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