Fast comparator circuit

Details Fast comparator circuit Fast comparator circuit

1995-09-13

1996-07-02

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327210, 327 57, H03K 5153, H03K 3356, G01R 1900

Patent

active

055326285

ABSTRACT:
A circuit for comparing an input signal having a first voltage to a reference signal having a second voltage to determine whether the input signal voltage is greater than or less than the reference signal voltage. In a preferred embodiment, the circuit essentially employs only four transistors (two inverters). First and second complimentary transistors are coupled in series to form the first inverter. Third and fourth complimentary transistors are coupled in series to form the second inverter. Between the first and second complimentary transistors is a first node and between the third and fourth transistors is a second node. The first and third transistors are coupled to together at a third node. The second and fourth transistors are coupled together at a fourth node. In a first phase of operation, the circuit receives the input voltage and the reference voltage. The input voltage and the reference voltage are applied to the first and second nodes using two switches until the first and second nodes have sampled the voltages (via parasitic capacitance). In a second phase of operation, the circuit operates as an amplifier. The two inverters amplify the difference in voltages at the first and second nodes by passing increasing current from the third node to the fourth node, which passes through both inverters. Next, in a third phase of operation, the circuit operates as a latch. A high logic voltage (V.sub.DD) is applied to the third node and a low logic voltage (V.sub.SS) is applied to the fourth node. At this point, if the input voltage is greater than the reference voltage, then the first node pulled-up to V.sub.DD and the second node pulled down to V.sub.SS. If the input voltage is less than the reference voltage, then the first node assumes the voltage V.sub.SS and the second node is pulled-up to V.sub.DD. Finally, in fourth phase of operation, the circuit outputs can be measured by sensing the voltages at the first and second nodes (in this phase, the outputs of the circuit).

REFERENCES:
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patent: 4558241 (1985-12-01), Suzuki et al.
patent: 4680735 (1987-07-01), Miyamoto et al.
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patent: 5226014 (1993-07-01), McMarus
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Uyemura, "Fundamentals of MOS Digital Integrated Circuits", Addison-Wesley Company, 1988, pp. 74-75.
Rahul Sarpeshkar, et al., "Mismatch Sensitivity of a Simultaneously Latched CMOS Sense Amplifier," IEEE Journal of Solid-State Circuits, vol. 26, No. 10, Oct., 1991, pp. 1413-1422.

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