Fast clock generator and clock synchronizer for logic derived cl

Details Fast clock generator and clock synchronizer for logic derived cl Fast clock generator and clock synchronizer for logic derived cl

1997-03-28

1999-07-13

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, 327162, H03K 1722, H03L 700

Patent

active

059231955

ABSTRACT:
A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal. The suspendable clock signal may be gated off in response to an input signal having a minimum duration of at least two clock cycles of the synchronous clock signal.

REFERENCES:
patent: 4973860 (1990-11-01), Ludwig
patent: 5001374 (1991-03-01), Chang
patent: 5418407 (1995-05-01), Frenkil
patent: 5764710 (1998-06-01), Cheng et al.

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