Boots – shoes – and leggings
Patent
1993-10-01
1995-01-17
Malzahn, David H.
Boots, shoes, and leggings
36471504, 3647151, G06F 501
Patent
active
053831420
ABSTRACT:
A method and processor design for detecting a specified bit pattern based on the contents of one or more registers, each register having a plurality of bits. The invention is well suited for parallel processing. The method begins by combining successive sets of contiguous bits to generate a state value and output value representative of the values in each set of contiguous bits. The state values and output values so generated become the values for level 1 of a hierarchy of state and output values. The manner in which the states are assigned and the number of states will, in general, depend on the specific bit pattern being sought. At each successive level in the hierarchy, sets of continuous output values and state values from the previous level are combined to generate the output values and state values for the level in question. The number of output and state values is reduced by at least a factor of two at each level of the hierarchy. The process is terminated when only one output value and state value remains. The final output value specifies the location of the first bit of the bit pattern sought in the original bit string when the final state indicates that the bit pattern has been found. The method may be implement by a processor that includes a hierarchical array of processing elements arranged as a plurality of ordered levels of processors. Each level of processors has one or more processing modules. Each processing module receives a plurality of state inputs and generates therefrom a state output. The processing modules in level 1 have their state inputs connected to selected bits in the registers and the processing modules in the k.sup.th level of the hierarchy have their state inputs connected to state outputs of processing modules in level (k-1).
REFERENCES:
patent: 4785421 (1988-11-01), Takahashi et al.
patent: 4864527 (1989-09-01), Peng et al.
patent: 4939683 (1990-07-01), van Heerden et al.
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5111415 (1992-05-01), Shackleford
patent: 5212699 (1993-05-01), Morita
Richard E. Ladner and Michael J. Fischer, "Parallel Prefix Computation", Journal of the Association for Computing Machinery, vol. 27, No. 4, Oct. 1980.
V. G. Oklobdzija, "Algorithmic Design of a Hierarchical and Modulator Leading Zero Detector Circuit", Electronic Letters 4 Feb. 1993, vol. 29, No. 3.
Belle Wei, Ph.D. Thesis, University of California, Berkeley, EECS Department, 1987, pp. 4 -11.
Hewlett--Packard Company
Malzahn David H.
LandOfFree
Fast circuit and method for detecting predetermined bit patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast circuit and method for detecting predetermined bit patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast circuit and method for detecting predetermined bit patterns will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-751982