Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-10-02
2003-12-02
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S702000
Reexamination Certificate
active
06658446
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an elementary chainable adder working at high frequencies, performing a binary summation of two input bits A and B and one carry input C.
2. Discussion of the Background
Since the binary sum can vary between 00 and 11, the adder has a least significant bit output SO and a most significant bit output CO (or carry output).
The truth table of an elementary chainable adder
10
, schematically shown in
FIG. 1
a
, is given by the table of
FIG. 1
b
showing all the possible binary states of the input bits A, B, C and the corresponding states of the least significant output SO and most significant output CO.
The elementary chainable adder
10
is a building block for adders that can sum up M words of N bits, M being an integer greater than or equal to
2
.
FIG. 2
shows a typical architecture
20
of an adder of this kind comprising elementary chainable adders
10
.
An elementary adder
12
processing the bits A(i), B(i), C(i) having the place value p, with i=0,1,2, . . . N−1, receives its carry input C from the carry output CO of the elementary adder
13
processing the bits with the place value (p−1), its own output CO feeding the carry input C of the elementary adder
14
processing the bits with the place value (p+1). The inputs A and B of the elementary adder may serve directly as inputs for another adder of the same type. This notion of chainability assumes a compatibility of the input and output levels.
Let tps be the propagation time between the inputs A or B, and the least significant value output SO and let tpc be the propagation time between the inputs A or B, and the carry output CO of an elementary chainable adder. For the sum of two N bit words, there should be a total time equal to N.tpc+tps. Thus, the propagation time of the complete structure depends on tpc.
The performance criteria sought for an adder module to be made in integrated circuit technology are chiefly:
propagation time
consumption
circuit working with supply voltages from 2.7 volts. The maximum voltage is fixed by the behaviour under voltage of the technology used.
chainability
output SO positioned before the carry CO (i.e. tpc<tps) low surface area on silicon
At present there are different types of adders. The CMOS adders have a very high density of integration and low power consumption. These types of CMOS circuits have a propagation time that is excessively great for applications requiring fast computation. The use of the faster ECL technology entails the drawbacks of high consumption and large surface area for the structure.
SUMMARY OF THE INVENTION
In order to overcome the drawbacks of the prior art, the invention proposes a chainable adder receiving three bits A, B, C to give two complementary sum outputs and two complementary carry outputs comprising:
a first stage with three differential pairs P
1
, P
2
, P
3
each receiving a respective bit A, B, C and its complement A*, B*, C*, the three pairs having common output arms and being powered by an identical current I, the output arms each comprising three resistors R
1
, R
2
, R
3
and R
4
, R
5
, R
6
in series connected to a reference potential, these resistors defining three intermediate nodes A
1
, A
2
, A
3
in the first arm, B
1
, B
2
, B
3
in the second arm, the carry outputs being taken at the nodes A
2
and B
2
,
a second stage comprising three other differential pairs P
4
, P
5
, P
6
whose inputs are connected to the nodes Al and B
3
for the pair P
4
, the nodes A
2
and B
2
for the pair P
5
and the nodes A
3
and B
1
for the pair P
6
, the pairs P
4
and P
6
each having a common arm with the pair P
5
and an arm that is not common, the sum outputs of the adder stage being each constituted by the combination, according to an “or” function, of the logic states appearing respectively on the non-common arm of one of the pairs P
4
and P
6
and on the common arm of the other pair.
The original structure of the adder according to the invention has the advantage of reducing the number of logic layers needed for the addition to the minimum. Indeed, the least significant output is obtained in two logic layers and the carry output is stabilized before the least significant output in a single layer. This substantially reduces the propagation time of the adder as compared with the prior art adders.
The term <<logic layer>> is understood here to mean the elementary stages that use the amplifier effect of the transistor (between its base and its collector) to go from input to output. This is by opposition to effects of the “follower” type which are also used here and are far speedier than the amplifier effects, and are therefore negligible compared with these effects in terms of propagation time.
Other advantages of this structure lie in the minimizing of the number of components used and in the reduction of consumption.
Hereinafter, the logic complement is indicated by an asterisk. In the drawings, it is conventionally represented by a bar above the name of the
BRIEF DISCUSSION OF THE DRAWINGS
The invention will be understood more clearly from the following detailed description made with reference to the appended drawings, of which:
FIG. 1
a
and
1
b
, already described, respectively represent an elementary prior art chainable adder and its truth table.
FIG. 2
, already described, shows a typical architecture of an adder that can sum of M words of N bits, comprising the elementary chainable adders of
FIG. 1
a
.
FIG. 3
shows an embodiment, according to the invention, of an elementary, chainable adder stage.
FIG. 4
shows a table of the levels and states of the first stage of the adder of FIG.
3
.
FIG. 5
shows a table of states of the second stage of the adder of FIG.
3
.
FIG. 6
shows a table of results of the adder of FIG.
3
.
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patent: 5444447 (1995-08-01), Wingender
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patent: 5499203 (1996-03-01), Grundland
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Le Tual Stephane
Simony Laurent
Wingender Marc
Atmel Grenoble S.A.
Ngo Chuong Dinh
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