Fast cascaded class AB bipolar output stage

Details Fast cascaded class AB bipolar output stage Fast cascaded class AB bipolar output stage

2002-05-28

2004-04-27

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S277000, C330S288000, C323S315000

Reexamination Certificate

active

06727758

ABSTRACT:

TECHNICAL FIELD
The invention relates to high voltage and power output circuits, and more particularly, to an improved cascaded configuration for a class AB bipolar output stage.
BACKGROUND AND SUMMARY OF THE INVENTION
High voltage and high power output circuits may be manufactured from bipolar output stages or bipolar structures. A typical class AR output stage utilizing bipolar structures is shown in FIG.
1
.
Usually, there are several important parameters relevant to the design of a output stage. Crossover distortion should be minimized in order to provide an accurate noise-free output signal. Additionally, it is desirable to reduce static power consumption of the output stage.
Over the years, numerous variations of cascaded class AB configurations have been developed. With respect to the large number of available such configurations, each has its own advantages and/or disadvantages. Several such prior art examples are discussed below.
FIG. 1
depicts a cascaded class AB buffer utilizing bipolar transistors and several diodes as shown. Notably, there are four static current paths
201
-
204
, leading to increased power consumption. As stated above, minimization of power consumption is a goal in class AB output stages. Thus, the arrangement of
FIG. 1
is suboptimal.
FIG. 2
shows a class C Darlington output stage with biasing resistors utilizing FET technology. The arrangement of
FIG. 2
would appear to consume less power than that of
FIG. 1
, owing to the fact that there are less current paths. It is noted however, that in the arrangement of
FIG. 2
, transistors M
3
and M
4
see the load through biasing resistors R
1
and R
2
. For purely capacitive loads, transistors M
3
and M
4
must be sized properly to prevent slowing down of the circuit. Often, this means utilizing larger transistors, with higher power consumption, than desirable. Thus, the larger transistors can make up for the reduction in current paths, and a relatively high power consuming device still results.
In addition to the foregoing power consumption problem, another problem in output stages is that of crossover distortion. A prior art known technique of minimizing crossover distortion is to utilize a feedback loop to cancel such distortion. However, the implementation of such a feedback loop also results in added power consumption.
In view of the above, there exists a need in the art for an improved circuit for minimizing required current and thus power consumption of the Class AB output stage while at the same time eliminating crossover distortion.
The above and other problems with the prior art are overcome in accordance with the present invention. The present invention includes a circuit having cascaded output stages utilizing three sets of FET devices. Of the three sets of FET devices, in a preferred embodiment, a first set includes four FETs, a second set includes a different four FETs, and a third set includes two FETs. Two of the transistors from the second set and the two transistors from the third set comprise one class AB stage, and the remaining two transistors from the second set and all four transistors from the first set comprise the second class AB stage. The two stages are cascaded in a manner that reduces the required size for the transistors as well as eliminating crossover distortion. The arrangement avoids such crossover distortion without the need for a feedback loop, thereby eliminating the additional components that would otherwise be required and also minimizing power dissipation.
The circuit has the further advantage of minimizing current paths, and thus power consumption, while permitting smaller size transistors to be used, even to drive relatively highly capacitive output loads.
Further advantages of the present invention will become clear from the following detailed description and drawings.


REFERENCES:
patent: 4267517 (1981-05-01), Iida et al.
patent: 6259280 (2001-07-01), Koelling

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