Fast carry generation adder having grouped carry muxes

Details Fast carry generation adder having grouped carry muxes Fast carry generation adder having grouped carry muxes

1996-09-11

1998-11-17

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

058386025

ABSTRACT:
An integrated circuit having a fast carry generation adder for adding together two input signals has an initial stage and two or more intermediate stages. The adder may also include a final stage. Each intermediate stage has a carry mux and these carry muxes are grouped together, for example, adjacent to the initial stage and adjacent to the first intermediate stage. By grouping the carry muxes together, for example, in a column below the initial stage, the fast carry generation adder may be both faster and smaller than conventional adders and may reduce or even eliminate the need for any buffering between successive carry muxes.

REFERENCES:
patent: 3553446 (1971-01-01), Kruy
patent: 4682303 (1987-07-01), Uya
patent: 5027311 (1991-06-01), Zion
patent: 5229959 (1993-07-01), Scriber
patent: 5272662 (1993-12-01), Scriber et al.
patent: 5471414 (1995-11-01), Kumar et al.

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