Fast capacitive-load driving circuit particularly memories

Details Fast capacitive-load driving circuit particularly memories Fast capacitive-load driving circuit particularly memories

1991-12-20

1994-02-01

Wambach, Margaret R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307263, 307268, 307572, 307576, 328 59, H03K 301, H03K 512

Patent

active

052834786

ABSTRACT:
A fast capacitive-load driving circuit for driving output nodes on an integrated circuit. This circuit reduces noise interference caused by parasitic inductance by lowering the inductance voltage on the power supply lines during the switching process. This invention includes a voltage ramp, a voltage-to-current converter, and an output buffer having at least one pull-down transistor. A further embodiment includes an output buffer possessing a pull-down and a pull-up transistor.

REFERENCES:
patent: 4182963 (1980-01-01), Yamado et al.
patent: 4216393 (1980-08-01), Gilliberg et al.
patent: 4504779 (1985-03-01), Haman
patent: 4698531 (1987-10-01), Jones
patent: 4797579 (1989-01-01), Lewis
patent: 4825099 (1989-04-01), Barton
IBM Tech. Disc. Bul. "Driver circuit having controllable inactive time" Bigbie et al. vol. 18 No. 9 Feb. 1976 pp. 2751-2752.
IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 88, New York, U.S., pp. 455-456.

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