Fast bist architecture with flexible standard interface

Details Fast bist architecture with flexible standard interface Fast bist architecture with flexible standard interface

1997-08-21

1999-02-16

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058727930

ABSTRACT:
A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

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Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, Mar. 1, 1995, (complete original booklet).

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